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《TI-SN74ACT3632：双512×36位时钟双向FIFO内存》 SN74ACT3632是一款由德州仪器（TI）生产的先进CMOS技术芯片，专为高速数据缓冲和传输设计。这款芯片包含了两个独立的512×36位时钟控制的双向FIFO（先进先出）内存，能够以相反的方向缓冲数据。该器件在通信、数据处理和接口控制等应用中表现出色。 SN74ACT3632支持两种自由运行的时钟信号CLKA和CLKB，它们可以是异步的，也可以是同步的，这使得该芯片能够在不同的时钟域中工作，提供灵活的数据同步机制。每个FIFO都配备了一个邮箱旁路寄存器，允许数据快速通过，优化了数据流的处理。该器件还具备可编程的“几乎满”（Almost-Full）和“几乎空”（Almost-Empty）标志，这些标志对于实时监控FIFO的状态至关重要，有助于避免溢出或空置的情况发生。此外，微处理器接口控制逻辑集成在芯片内，简化了与微处理器系统的接口设计。 SN74ACT3632提供了IRA、ORA、AEA和AFA四个同步标志，它们分别由CLKA同步，用于检测读写活动。同样，IRB、ORB、AEB和AFB标志则由CLKB同步，为第二个FIFO提供相同的功能。这些标志的同步性确保了在不同时钟域之间数据交换的精确性。在硬件层面，SN74ACT3632采用0.8微米的低功耗工艺制造，支持高达67MHz的时钟频率，实现了11ns的快速访问时间，这在高频率操作下显得尤为关键。为了满足不同应用场景的需求，该芯片提供了120引脚的薄型四边扁平封装（PCB）和132引脚的塑料四边扁平封装（PQ）。 TI-SN74ACT3632是一款高效能、高灵活性的双向FIFO内存解决方案，适用于需要高速数据处理和同步的应用。其低功耗特性、强大的同步功能以及与SN74ACT3622和SN74ACT3642的引脚兼容性，使得它成为系统设计中的理想选择。不过，用户需要注意的是，德州仪器在其产品数据表的末尾提到了关于产品可用性、标准保修和在关键应用中的使用免责声明，使用者在实际应用中应仔细阅读并遵循这些信息。

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SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Two Independent 512 × 36 Clocked FIFOs

Buffering Data in Opposite Directions

Mailbox-Bypass Register for Each FIFO

Programmable Almost-Full and

Almost-Empty Flags

Microprocessor Interface Control Logic

IRA, ORA, AEA, and AFA Flags

Synchronized by CLKA

IRB, ORB, AEB, and AFB Flags

Synchronized by CLKB

Low-Power 0.8-µm Advanced CMOS

Technology

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 11 ns

Pin-to-Pin Compatible With the

SN74ACT3622 and SN74ACT3642

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

PCB PACKAGE

(TOP VIEW)

A35

A34

A33

A32

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

A12

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

B15

B14

B13

B12

GND

CLKA

ENA

GND

A11

A10

CSA

IRA

ORA

MBA

AFA

FS0

GND

FS1

RST2

MBB

MBF1

AEB

ORB

IRB

W/RA

GND

CSB

W/RB

ENB

CLKB

B10

RST1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

AEA

AFB

GND

B11

MBF2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The SN74ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock

frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port

SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full

conditions and two programmable flags, almost full (AF

) and almost empty (AE) to indicate when a selected

number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit

mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more

devices can be used in parallel to create wider datapaths.

The SN74ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asynchronous or coincident. The enables for each port

are arranged to provide a simple bidirectional interface between microprocessors and/or buses with

synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA

, AFB) flag of a FIFO are two-stage synchronized to the

port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA

, AEB) flag

of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the AF

and AE flags of both FIFOs can be programmed from port A.

The SN74ACT3632 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

•

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

•

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors

(literature number

SCAA005)

•

Metastability Performance of Clocked FIFOs

(literature number SCZA004)

SN74ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.

AEA

(port A)

Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2

is less than or equal to the value in the almost-empty A offset register, X2.

AEB

(port B)

Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1

is less than or equal to the value in the almost-empty B offset register, X1.

AFA

(port A)

Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in

FIFO1 is less than or equal to the value in the almost-full A offset register, Y1.

AFB

(port B)

Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in

FIFO2 is less than or equal to the value in the almost-full B offset register, Y2.

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. IRA, ORA, AFA

, and AEA are all synchronized to the low-to-high transition of CLKA.

CLKB I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. IRB, ORB, AFB

, and AEB are synchronized to the low-to-high transition of CLKB.

CSA

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

A0–A35 outputs are in the high-impedance state when CSA

is high.

CSB

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

B0–B35 outputs are in the high-impedance state when CSB

is high.

ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1, FS0 I

Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0

or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO AF

and

flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2 go high, the

first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.

IRA

(port A)

Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes

to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA

after reset.

IRB

(port B)

Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes

to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB

after reset.

MBA I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the

A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects

FIFO2 output-register data for output.

MBB I

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO1 output-register data for output.

MBF1

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes

to the mail1 register are inhibited while MBF1

is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B

read is selected and MBB is high. MBF1

is set high when FIFO1 is reset.

MBF2

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes

to the mail2 register are inhibited while MBF2

is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A

read is selected and MBA is high. MBF2

is also set high when FIFO2 is reset.

ORA

(port A)

Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty and

reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA

is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to

empty memory.

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