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TI-DS125BR111.pdf
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以太网转接驱动器
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VDD
INA+
INA-
AD0/EQA0
AD1/EQA1
ENSMB
SCL/VODB_DB
(2)
READEN/VOD_SEL
DONE/RXDET
SDA/VODA_DB
(2)
OUTA+
OUTA-
(DAP) GND
(5)
(1) Schematic requires different connections for SMBus Master Mode and Pin Mode
(2) SMBus signals need to be pulled up elsewhere in the system
(3) PWDN pin can alternatively be driven by a control device (i.e. FPGA)
(4) Schematic requires different connections for 3.3 V mode
(5) A minimum of 4 vias are recommended for proper thermal and electrical performance
DS125BR111
VDD
10F
(1x)
0.1F
(2x)
SMBus
Slave
Mode
(1)
2.5V
OUTB+
OUTB-
INB+
INB-
VDD_SEL
VIN
2.5 V
Mode
(4)
1 N
Address
straps (pull-up
or pull-down)
To system
SMBus
AD2/EQB1
AD3/EQB0
RES
VDD
PWDN
(3)
Normal
operation
1F
(1x)
SD_TH
3.3V
4.7 N
4.7 N
Product
Folder
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DS125BR111
ZHCSCR3C –OCTOBER 2012–REVISED AUGUST 2014
DS125BR111 具具有有均均衡衡器器的的低低功功耗耗 12.5Gbps 1 通通道道线线性性中中继继器器
1 特特性性 3 说说明明
1
• 每通道 65mW(典型值)低功耗
DS125BR111 是一款超低功耗的高性能中继器/转接驱
动器,旨在支持高达 12.5Gbps 的 1 通道高速接口。
• 支持链路协商
6GHz 时,接收器的连续时间线性均衡器 (CTLE) 可在
• 支持带外 (OOB) 信令
每个通道上提高 3-10dB。 在 SAS-3 或 PCIe Gen-3
• 高级信号调节 I/O
应用中工作时,DS125BR111 保留发射信号特性,从
– 6GHz 时,接收高达 10dB 的连续时间线性均衡
器 (CTLE)
而使得主机控制器和端点能够协商发射均衡器系数。
– 线性输出驱动器
链接协商协议的透明度能够最大程度增加互连通道内器
– 输出电压范围超过 1200mV
件实体布局的灵活性并提高通道的总体性能。
• 可通过引脚选择、EEPROM 或 SMBus 接口进行编
可通过引脚、软件(SMBus 或 I2C)来轻松应用相关
程
可编程设置,或者通过外部 EEPROM 来载入此设置。
• 单电源电压:2.5V 或 3.3V
在 EEPROM 模式下,配置信息在加电时被自动载入,
• -40°C 至 85°C 的工作温度范围
这样就免除了对于外部微控制器或软件驱动程序的需
• 4mm x 4mm 24 引脚超薄型四方扁平无引线
要。
(WQFN) 封装内的直通引脚分配
器器件件信信息息
(1)
2 应应用用
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
• SAS-1/2/3 和 SATA-1/2/3
DS125BR111 WQFN (24) 4.00mm x 4.00mm
• PCI Express 1/2/3
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
• 其它速率高达 12.5Gbps 的专有接口
4 简简化化电电路路原原理理图图
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNLS430
DS125BR111
ZHCSCR3C –OCTOBER 2012–REVISED AUGUST 2014
www.ti.com.cn
目目录录
8.2 Functional Block Diagram ....................................... 13
1 特特性性.......................................................................... 1
8.3 Feature Description................................................. 14
2 应应用用.......................................................................... 1
8.4 Device Functional Modes........................................ 14
3 说说明明.......................................................................... 1
8.5 Programming .......................................................... 17
4 简简化化电电路路原原理理图图........................................................ 1
8.6 Register Maps......................................................... 24
5 修修订订历历史史记记录录 ........................................................... 2
9 Application and Implementation ........................ 32
6 Pin Configuration and Functions......................... 3
9.1 Application Information............................................ 32
7 Specifications......................................................... 6
9.2 Typical Application ................................................. 34
7.1 Absolute Maximum Ratings ...................................... 6
10 Power Supply Recommendations ..................... 36
7.2 Handling Ratings....................................................... 6
11 Layout................................................................... 37
7.3 Recommended Operating Conditions....................... 6
11.1 Layout Guidelines ................................................. 37
7.4 Thermal Information.................................................. 6
11.2 Layout Example .................................................... 37
7.5 Electrical Characteristics........................................... 7
12 器器件件和和文文档档支支持持 ..................................................... 38
7.6 Electrical Characteristics — Serial Management Bus
12.1 商标 ....................................................................... 38
Interface .................................................................. 10
12.2 静电放电警告......................................................... 38
7.7 Timing Requirements.............................................. 10
12.3 术语表 ................................................................... 38
7.8 Typical Characteristics............................................ 12
13 机机械械封封装装和和可可订订购购信信息息 .......................................... 38
8 Detailed Description............................................ 13
8.1 Overview ................................................................. 13
5 修修订订历历史史记记录录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2014) to Revision C Page
• 已更改 已将数据表流程和版面布局更改为符合全新的 TI 标准。 添加了以下章节:应用和实施;电源相关建议;布
局;器件和文档支持;机械、封装和订购信息........................................................................................................................ 1
Changes from Revision A (January 2014) to Revision B Page
• 已更改 特性............................................................................................................................................................................. 1
Changes from Original (April 2013) to Revision A Page
• 已更改 已将国标数据表格式改为 TI 格式................................................................................................................................ 1
2 Copyright © 2012–2014, Texas Instruments Incorporated
INB+
INB-
OUTA+
VDD_SEL
VIN
18
INA+
INA-
17
14
13
16
RES
VOD_SEL / READEN
RXDET / DONE
SD_TH
OUTB+
OUTB-
OUTA-
SMBUS AND
CONTROL
15
VDD
24
23
22
21
20
19
11
12
8
10
9
7
EQB1/AD2
ENSMB
1
2
5
6
3
SCL/VODB_DB
EQB0/AD3
SDA/VODA_DB
4
VDD
PWDN
AD1/EQA1
AD0/EQA0
DS125BR111
www.ti.com.cn
ZHCSCR3C –OCTOBER 2012–REVISED AUGUST 2014
6 Pin Configuration and Functions
24 Pin
Package RTW
Top View
The center DAP on the package bottom is the only device GND connection. This pad must be connected to
GND through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
DIFFERENTIAL HIGH SPEED I/O
Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination
INB+, INB- 11, 12 I resistor connects INB+ to VDD and INB- to VDD when enabled by RXDET control logic.
AC coupling required on high-speed I/O
OUTB+, Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs.
20, 19 O
OUTB- AC coupling required on high-speed I/O
Inverting and non-inverting CML differential inputs to the equalizer. On-chip 50 Ω termination
INA+, INA- 24, 23 I resistor connects INA+ to VDD and INA- to VDD when enabled by RXDET control logic.
AC coupling required on high-speed I/O
OUTA+, Inverting and non-inverting 50 Ω driver outputs. Compatible with AC coupled CML inputs.
7, 8 O
OUTA- AC coupling required on high-speed I/O
Copyright © 2012–2014, Texas Instruments Incorporated 3
DS125BR111
ZHCSCR3C –OCTOBER 2012–REVISED AUGUST 2014
www.ti.com.cn
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
CONTROL PINS — SHARED (LVCMOS)
System Management Bus (SMBus) enable Pin
I, 4-LEVEL, Tie 1 kΩ to VDD = Register Access SMBus Slave mode
ENSMB 3
LVCMOS FLOAT = Read External EEPROM (Master SMBus Mode)
Tie 1 kΩ to GND = Pin Mode
ENSMB = Float or 1 (SMBus MODEs)
I, LVCMOS, ENSMB Master or Slave mode
SCL 5 O, OPEN SMBus clock input Pin is enabled (slave mode).
Drain Clock output when loading EEPROM configuration (master mode).
ENSMB Master or Slave mode
I, LVCMOS,
The SMBus bidirectional SDA Pin is enabled. Data input or open drain output. External pull-
SDA 4 O, OPEN
up required as per SMBus protocol (typically in the 2 kΩ to 5 kΩ range). This pin is 3.3 V-
Drain
tolerant.
ENSMB Master or Slave mode
AD0-AD3 10, 9, 2, 1 I, LVCMOS SMBus Slave Address Inputs. In SMBus mode, these Pins are the user set SMBus slave
address inputs.
ENSMB = Float: When using an External EEPROM, a logic low on this pin starts the load
from the external EEPROM
READEN 17 I, LVCMOS ENSMB = 1: When using SMBus Slave Mode the VOD_SEL/READEN pin must be tied Low
for the AD[3:0] to be active. If this pin is tied High or Floated an address of 0xB0 will be used
for the DS125BR111.
When using an External EEPROM (ENSMB = Float), Valid Register Load Status Output
DONE 18 O, LVCMOS HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0 and EQB0 control the level of equalization of the A/B directions. The Pins are defined
EQA0 10 I, 4-LEVEL,
as EQx0 only when ENSMB is de-asserted (low). When ENSMB goes high the SMBus
EQB0 1 LVCMOS
registers provide independent control of each channel. See Table 4.
EQA1 9 I, 4-LEVEL, EQA1 and EQB1 are not used in the DS125BR111 design. These pins should always be tied
EQB1 2 LVCMOS to GND.
VODA_DB controls the CHA output amplitude dynamic range, for SAS and PCIe applications
I, 4-LEVEL, it should be held Low. The Pin is defined as VODA_DB only when ENSMB is de-asserted
VODA_DB 4
LVCMOS (low). When ENSMB goes high the SMBus registers provide control of each channel, pin 4 is
converted to SDA. See Table 5.
VODB_DB controls the CHB output amplitude dynamic range, for SAS and PCIe applications
I, 4-LEVEL, it should be held Low. The Pin is defined as VODB_DB only when ENSMB is de-asserted
VODB_DB 5
LVCMOS (low). When ENSMB goes high the SMBus registers provide control of each channel, pin 5 is
converted to SCL. See Table 5.
Controls the internal Signal Detect Threshold. This detection threshold is for system debug
I, 4-LEVEL,
SD_TH 14 only and does not control the high speed datapath.
LVCMOS
See Table 3.
I, 4-LEVEL, VOD_SEL controls the low frequency ratio of input voltage to output voltage amplitude. See
VOD_SEL 17
LVCMOS Table 5.
The RXDET Pin controls the receiver detect function. Depending on the input level, a 50 Ω or
> 50 kΩ termination to the power rail is enabled. In a SAS/SATA system RXDET should be
set to a Logic "1" state to keep the termination always enabled.
I, 4-LEVEL,
RXDET 18 The RXDET pin only controls the RXDET function in PIN MODE. PCIe applications
LVCMOS
which require SMBus Mode functionality must utilize a specific register write
sequence documented in PCIe Applications . If this sequence is not utilized, SMBus
configuration modes will default the input terminations to active (50 Ω). See Table 2 .
4 Copyright © 2012–2014, Texas Instruments Incorporated
DS125BR111
www.ti.com.cn
ZHCSCR3C –OCTOBER 2012–REVISED AUGUST 2014
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
I, 4-LEVEL, Reserved:
RES 13
LVCMOS This input must be left Floating.
Controls the internal regulator
VDD_SEL 16 I, FLOAT Float = 2.5 V mode
Tie GND = 3.3 V mode
Tie High = Low power - power down
PWDN 6 I, LVCMOS Tie GND = Normal Operation
See Table 2.
POWER (See Figure 11)
In 3.3 V mode, feed 3.3 V to VIN
VIN 15 Power
In 2.5 V mode, leave floating.
Power supply pins CML/analog
VDD 21, 22 Power 2.5 V mode, connect to 2.5 V
3.3 V mode, decouple each VDD pin with 0.22 µF cap to GND
GND DAP Power Ground pad (DAP - die attach pad).
Copyright © 2012–2014, Texas Instruments Incorporated 5
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