TI-DS64BR401.pdf

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IA_1+, IA_1-, 12, 13 gated on-chip 50Ω termination resistor connects INA_n+ to VDD and

IA_2+, IA_2-, 15, 16 INA_n- to VDD when enabled.

IA_3+, IA_3- 17, 18

OA_0+, OA_0-, 35, 34 O, LPDS Inverting and non-inverting low power differential signaling (LPDS) 50Ω

OA_1+, OA_1-, 33, 32 outputs with de-emphasis. Compatible with AC coupled CML inputs.

OA_2+, OA_2-, 31, 30

OA_3+, OA_3- 29, 28

IB_0+, IB_0- , 45, 44 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A

IB_1+, IB_1-, 43, 42 gated on-chip 50Ω termination resistor connects INB_n+ to VDD and

IB_2+, IB_2-, 40, 39 INB_n- to VDD when enabled.

ENSMB 48 I, LVCMOS w/ System Management Bus (SMBus) enable pin.

internal pull- When pulled high provide access internal digital registers that are a

down means of auxiliary control for such functions as equalization, de-

emphasis, VOD, rate, and idle detection threshold.

When pulled low, access to the SMBus registers are disabled and

SMBus function pins are used to control the Equalizer and De-Emphasis.

Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND

CONFIGURATION REGISTERS section and ELECTRICAL

CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE for

detail information.

ENSMB = 1 (SMBUS MODE)

O, Open Drain The SMBus bi-directional SDA pin is enabled. Data input or open drain

Refer to R

in the SMBus specification.

AD0–AD3 54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1

internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user

down set SMBus slave address inputs. See section — SYSTEM

MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS

for additional information.

ENSMB = 0 (NORMAL PIN MODE)

EQA0, EQA1 20, 19 I, Float, EQA/B, 3–level controls the level of equalization of the A/B sides. The

EQB0, EQB1 46, 47 LVCMOS EQA/B pins are active only when ENSMB is de-asserted (Low). Each of

the 4 A/B channels have the same level unless controlled by the SMBus

provide independent control of each lane. See Table 5

RATE 21 I, Float, RATE, 3–level controls the pulse width of de-emphasis of the output.

LVCMOS RATE = 0 forces 3 Gbps,

RATE = 1 forces 6 Gbps,

RATE = Float enables auto rate detection and the pulse width (pull-back)

is set appropriately after each exit from IDLE. This requires the transition

from IDLE to ACTIVE state — OOB signal. See Table 5

TXIDLEA,TXIDLEB 24, 25 I, Float, TXIDLEA/B, 3–level controls the driver output.

VOD0, VOD1 22, 23 I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage level.

internal pull- VOD[1:0] = 00 sets output VOD = 600 mV (Default)

down VOD[1:0] = 01 sets output VOD = 800 mV

VOD[1:0] = 10 sets output VOD = 1000 mV

VOD[1:0] = 11 sets output VOD = 1200 mV

PWDN 52 I, LVCMOS PWDN = 0 enables the device (normal operation).

PWDN = 1 disables the device (low power mode).

Pin must be driven to a logic low at all times for normal operation

SD_TH 27 I, ANALOG Threshold select pin for electrical idle detect threshold. Float pin for

VDD 9, 14, 36, 41, 51 Power Power supply pins. 2.5 V +/-5%

thermal performance of the package.

NC 26 No Connect — Leave pin open

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.