TI-DS125BR800A.pdf资源-CSDN文库

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【TI-DS125BR800A.pdf】是一款由德州仪器（TI）推出的低功耗12.5-Gbps 8通道（单向）重传器，专门设计用于支持PCIe、SAS以及其他高速接口串行协议，最高可达12.5 Gbps的数据传输速率。这款器件在确保系统互操作性的同时，还提供了出色的信号调理功能，以应对各种接口介质带来的挑战。主要特点： 1. **低功耗设计**：每个通道的典型功耗仅为65毫瓦，且有选项可以关闭未使用的通道，进一步降低功耗。 2. **输入均衡化（CTLE）**：接收端的连续时间线性均衡器能提供高达+30 dB的增益（针对12.5 Gbps时为6.25 GHz），有效补偿因互符号干扰（ISI）引起的链路损耗，如30英寸以上背板走线或8米以上的铜缆。 3. **透明的链路训练管理**：对于PCIe和SAS协议，DS125BR800A允许主机控制器和终端设备无缝优化全链路并协商发送均衡器系数，确保与最小延迟的系统级互操作性。 4. **高级信号调理功能**： - **发射端去加重（Tx De-Emphasis）**：可调节高达-12 dB，用于补偿输出侧剩余的通道衰减。 - **输出电压控制**：范围为700 - 1300 mV，有助于优化信号质量。 5. **配置接口**：提供引脚选择、EEPROM或SMBus接口，便于设备配置。 6. **单一电源电压**：支持2.5 V或3.3 V，简化了电源管理。 7. **宽工作温度范围**：可在-40°C到85°C的环境中稳定工作，增强了应用的环境适应性。 8. **高ESD防护等级**：具备3-kV人体模型（HBM）静电放电保护等级，提高了系统的抗干扰能力。 9. **流线型引脚布局**：采用54引脚LLP封装（尺寸为10 mm x 5.5 mm，0.5 mm间距），便于布局和布线。 10. **支持的协议**：包括PCI Express（PCIe）Gen-3和Serial Attached SCSI（SAS）等高速接口标准。 TI-DS125BR800A是专为高速数据传输设计的一款高效能、低功耗的信号增强器，它能够通过精确的信号调理技术，在复杂的系统环境中实现可靠、高速的数据传输，确保了系统的稳定性和兼容性。

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DS125BR800A

www.ti.com

SNLS467 –NOVEMBER 2013

Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input Equalization

Check for Samples: DS125BR800A

FEATURES

DESCRIPTION

The DS125BR800A is an extremely low-power high-

• Proven System Interoperability

performance multi-protocol repeater/redriver designed

• Comprehensive multi-protocol Repeater

to support eight channels of PCIe, SAS, and other

Family

high-speed interface serial protocols up to 12.5 Gbps.

• Low 65-mW/Channel (Typ) Power

The receiver's continuous time linear equalizer

(CTLE) provides a boost of up to +30 dB at 6.25 GHz

Consumption, With Option to Power Down

(12.5 Gbps) in each of its eight channels and is

Unused Channels

capable of opening an input eye that is completely

• Transparent Management of Link Training

closed due to inter symbol interference (ISI) induced

Protocol for PCIe and SAS

by interconnect medium such as 30in+ backplane

• Advanced Signal Conditioning Features

traces or 8m+ copper cables, hence enabling host

controllers to ensure an error free end-to-end link.

– Rx CTLE up to 30 dB (24 dB for SAS3)

The strong linear equalization maximizes interconnect

– Tx De-Emphasis up to -12 dB

channel extension when the DS125BR800A is placed

– Tx Output Voltage Control: 700 - 1300 mV

with the majority of channel loss on the devices input

side. Adjustable transmit de-emphasis and output

• Device Configuration Interface:

voltage amplitude help to compensate for the

– Pin Selection, EEPROM, or SMBus Interface

remaining channel attenuation on the output side.

• Single Supply Voltage: 2.5 V or 3.3 V

When operating in SAS-3 and PCIe Gen-3 mode, the

• −40°C to 85°C Operating Temperature Range

DS125BR800A transparently allows the host

• 3-kV HBM ESD Rating

controller and the end point to optimize the full link

and negotiate transmit equalizer coefficients. This

• Flow-Thru Pinout: 54-Pin LLP (10 mm x 5.5

seamless management of the link training protocol

mm, 0.5 mm pitch)

ensures system level interoperability with minimum

• Supported Protocols

latency. With a low power consumption of 65

– SAS/SATA

mW/channel (typ) and option to turn-off unused

channels, the DS125BR800A enables energy efficient

– PCIe

system design. A single supply of 3.3 V or 2.5 V is

– Other Proprietary Interface up to 12.5 Gbps

required to power the device.

The programmable settings can be applied easily via

pins, software (SMBus or I2C) or loaded via an

external EEPROM. When operating in the EEPROM

mode, the configuration information is automatically

loaded on power up, which eliminates the need for an

external microprocessor or software driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS125BR800A

SNLS467 –NOVEMBER 2013

www.ti.com

Table 1. Pin Descriptions

(1)

Pin Name Pin Number I/O, Type Pin Description

Differential High Speed I/O's

INB_0+, INB_0-,INB_1+, 1, 2, 3, 4, I Inverting and non-inverting CML differential inputs to the equalizer. On-

INB_1-,INB_2+, INB_2- 5, 6, 7, 8, chip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to

,INB_3+, INB_3- VDD when enabled.

AC coupling required on high-speed I/O

INA_0+, INA_0-,INA_1+, 10, 11, 12, 13, I Inverting and non-inverting CML differential inputs to the equalizer. On-

INA_1-,INA_2+, INA_2- 15, 16, 17, 18 chip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to

,INA_3+, INA_3- VDD when enabled.

AC coupling required on high-speed I/O

OUTB_0+, OUTB_0-, 45, 44, 43, 42, O Inverting and non-inverting 50Ω driver outputs with de-emphasis.

OUTB_1+, OUTB_1-, 40, 39, 38, 37 Compatible with AC coupled CML inputs.

OUTB_2+, OUTB_2-, AC coupling required on high-speed I/O

OUTB_3+, OUTB_3-

OUTA_0+, OUTA_0-, 35, 34, 33, 32, O Inverting and non-inverting 50Ω driver outputs with de-emphasis.

OUTA_1+, OUTA_1-, 31, 30, 29, 28 Compatible with AC coupled CML inputs.

OUTA_2+, OUTA_2-, AC coupling required on high-speed I/O

OUTA_3+, OUTA_3-

Control Pins — Shared (LVCMOS)

ENSMB 48 I, 4-LEVEL System Management Bus (SMBus) enable pin

Tie 1kΩ to VDD = Register Access SMBus Slave Mode

FLOAT = Read External EEPROM (Master SMBUS Mode)

Tie 1kΩ to GND = Pin Mode

ENSMB = 1 (SMBUS MODE)

SCL 50 I, LVCMOS ENSMB Master or Slave mode

O, OPEN Drain SMBUS clock input is enabled (slave mode).

Clock output when loading EEPROM configuration (master mode).

SDA 49 I, LVCMOS, ENSMB Master or Slave mode

O, OPEN Drain The SMBus bidirectional SDA pin is enabled. Data input or open drain

(pull-down only) output.

AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB Master or Slave mode

SMBus Slave Address Inputs. In SMBus mode, these pins are the user

set SMBus slave address inputs.

READ_EN 26 I, LVCMOS When using an External EEPROM, a transition from high to low starts

the load from the external EEPROM

ENSMB = 0 (PIN MODE)

EQA0, EQA1, 20, 19, I, 4-LEVEL EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.

EQB0, EQB1 46, 47 The pins are active only when ENSMB is de-asserted (low). The 8

channels are organized into two banks. Bank A is controlled with the

EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When

ENSMB goes high the SMBus registers provide independent control of

each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3

inputs. See Table 3.

DEMA0, DEMA1, 49, 50, I, 4-LEVEL DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output

DEMB0, DEMB1 53, 54 driver. The pins are only active when ENSMB is de-asserted (low). The 8

channels are organized into two banks. Bank A is controlled with the

DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When

ENSMB goes high the SMBus registers provide independent control of

each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA

and DEMB[1:0] pins are converted to AD0, AD1 inputs.

See Table 4.

MODE 21 I, 4-LEVEL MODE control pin selects operating modes.

Tie 1kΩ to GND = GEN 1,2 and SAS/SATA (up to 6 Gbps)

FLOAT = AUTO Rate Select (for PCIe)

Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis

Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis

See Table 7

(1) LVCMOS inputs without the "FLOAT" conditions must be driven to a logic low or high at all times or operation is not guaranteed.

Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.

For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.

For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.

Product Folder Links: DS125BR800A

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