TI-DS10BR150.pdf
需积分: 10 142 浏览量
2023-02-08
23:14:48
上传
评论 4
收藏 952KB PDF 举报
ASIC / FPGA
CML
LVDS
LVPECL
ASIC / FPGA
LVDS
BR150
DS10BR150
www.ti.com
SNLS252D –APRIL 2007–REVISED APRIL 2013
DS10BR150 1.0 Gbps LVDS Buffer / Repeater
Check for Samples: DS10BR150
1
FEATURES
DESCRIPTION
The DS10BR150 is a single channel 1.0 Gbps LVDS
2
• DC - 1.0 Gbps Low Jitter, High Noise
buffer optimized for high-speed signal transmission
Immunity, Low Power Operation
over lossy FR-4 printed circuit board backplanes and
• On-chip 100Ω Input and Output Termination
balanced cables. Fully differential signal paths ensure
Minimizes Insertion and Return Losses,
exceptional signal integrity and noise immunity.
Reduces Component Count and Minimizes
Wide input common mode range allows the receiver
Board Space
to accept signals with LVDS, CML and LVPECL
• 7 kV ESD on LVDS I/O Pins Protects Adjoining
levels; the output levels are LVDS. A very small
Components
package footprint requires a minimal space on the
board while the flow-through pinout allows easy board
• Small 3 mm x 3 mm 8-WSON Space Saving
layout. The differential inputs and outputs are
Package
internally terminated with a 100Ω resistor to lower
device input and output return losses, reduce
APPLICATIONS
component count and further minimize board space.
• Clock and Data Buffering
• OC-12 / STM-4
• FireWire 800
Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
剩余16页未读，继续阅读
资源评论
