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VDD
ADDR0
ADDR1
SDC
(1)
READ_EN_N ALL_DONE_N
SDA
(1)
GND
(1) SMBus signals need to be pulled up elsewhere in the system.
Float for SMBus Slave
mode, or connect to next
GHYLFH¶V5($'_EN_N for
SMBus Master mode
VDD
1 F
(2x)
0.1 F
(4x)
SMBus Slave
mode
SMBus
Slave mode
2.5 V
EN_SMB
Address straps
(pull-up, pull-down, or float)
1 NŸ
To system SMBus
RX7P
RX7N
TX7P
TX7N
RX0P
RX0N
TX0P
TX0N
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本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS544
DS280BR820
ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019
DS280BR820 低低功功耗耗 28Gbps 8 通通道道线线性性中中继继器器
1
1 特特性性
1
• 八通道多协议线性均衡器,可支持传输速率高达
28Gbps 的接口
• 低功耗:93mW/通道(典型值)
• 无需散热器
• 无缝支持链路协商、自动协商和前向纠错 (FEC) 直
通功能的直线均衡
• 扩展通道长度,超出正常专用集成电路 (ASIC) 到
ASIC 性能 17dB+
• 超低延迟:100ps(典型值)
• 低附加随机抖动
• 采用集成 Rx 和 Tx 交流耦合电容的小型 8mm x
13mm 小型球状引脚栅格阵列 (BGA) 封装,可实现
简易直通路由
• 独特的引脚分配支持在封装下对高速信号进行路由
• 提供引脚兼容的重定时器
• 2.5V±5% 单电源
• 运行温度范围:–40°C 至 +85°C
2 应应用用
• 背板和中板长度延长
• 用于光纤铜缆和无源铜缆 (100G-SR4/LR4/CR4) 的
前端口眼图开启器
• QSFP28、SFP28、CFP2、CFP4、CDFP
3 说说明明
DS280BR820 是一款超低功耗、高性能八通道线性均
衡器,支持数据传输速率高达 28Gbps 的多速率、多
协议接口。该器件可用于扩展长度范围并提高背板、前
端口和芯片至芯片应用的高速串行链路的稳定性。 应
用。
DS280BR820 均衡器的线性特质保留了发射信号的特
性,因此允许主机与链路合作伙伴 ASIC 自由协商发射
均衡器系数 (100G-CR4/KR4)。这种链路协商协议的透
明管理有助于在对延迟影响最小的情况下实现系统级互
操作性。每条通道独立运行,允许 DS280BR820 进行
独立信道前向纠错 (FEC)。
DS280BR820 将小型封装尺寸、经优化的高速信号退
出和引脚兼容的重定时器相结合,使其成为高密度背板
应用的 理想选择。。凭借简化的均衡控制、低功耗和
超低附加抖动特性,该器件适用于 100G-
SR4/LR4/CR4 等前端接口。8mm x 13mm 小型封装
适用于 QSFP、SFP、CFP2、CFP4 和 CDFP 等多种
标准前端口连接器,并且无需散热器。
集成交流耦合电容(Rx 侧)免除了集成电路板 (PCB)
对于外部电容的需求。DS280BR820 具备一个单电
源,能够最大限度地降低外部组件的数量。这些 特性
降低了 PCB 布局布线复杂度以及物料清单 (BOM) 成
本。
引脚兼容的重定时器可用于距离较长的 应用。
DS280BR820 可通过 SMBus 或外部 EEPROM 进行
配置。单个 EEPROM 最多可由 16 个器件共享。
器器件件信信息息
(1)
器器件件型型号号 封封装装 封封装装尺尺寸寸((标标称称值值))
DS280BR820 nFBGA (135) 8.0mm x 13.0mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简简化化电电路路原原理理图图
2
DS280BR820
ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
Copyright © 2016–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Electrical Characteristics – Serial Management Bus
Interface ................................................................... 12
6.7 Timing Requirements – Serial Management Bus
Interface ................................................................... 12
6.8 Typical Characteristics............................................ 13
7 Detailed Description............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 18
7.6 Register Maps ........................................................ 19
8 Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Applications ............................................... 29
8.3 Initialization Set Up ................................................ 41
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Examples................................................... 42
11 器器件件和和文文档档支支持持 ..................................................... 45
11.1 文档支持................................................................ 45
11.2 接收文档更新通知 ................................................. 45
11.3 商标 ....................................................................... 45
11.4 静电放电警告......................................................... 45
11.5 Glossary................................................................ 45
4 修修订订历历史史记记录录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision A (October 2017) to Revision B Page
• 首次公开发布 ......................................................................................................................................................................... 1
Ground pin
High-speed pin
Power pin
Control/Status pin
No connect on
package
Test pin
J
H
G
F
E
D
C
B
A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
J
H
G
F
E
D
C
B
A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GND
GND
GND
GND
GND GND GND GND GND
GND
GND
GND
GND
GND
GND
GND GND GND
GNDGND
GND
GNDGND
GND GND GND GND GND GND GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND GND GND GND
GND
GND
GNDGNDGND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD VDD VDD VDD
VDD
VDD
TX6N
TX6P TX7N
TX7P
TX0N
TX0P
RX0P
RX0N
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
RX1P
RX1N
RX2P
RX2N
RX3P
RX3N
TX4N
TX4P
TX5N
TX5P
RX4P
RX4N
RX5P
RX5N
RX6P
RX6N
RX7P
RX7N
CAL_
CLK_
OUT
ADDR
1
ADDR
0
SDA
SDC
READ
_EN_
N
EN_S
MB
CAL_
CLK_
IN
ALL_
DONE
_N
INT_N
(NC)
TEST
1
TEST
0
3
DS280BR820
www.ti.com.cn
ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019
Copyright © 2016–2019, Texas Instruments Incorporated
5 Pin Configuration and Functions
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/O
RX0N B15 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX0P C15 Input
RX1N A13 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX1P B13 Input
RX2N A11 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX2P B11 Input
RX3N A9 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX3P B9 Input
RX4N A7 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX4P B7 Input
RX5N A5 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX5P B5 Input
RX6N A3 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX6P B3 Input
RX7N B1 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
RX7P C1 Input
TX0N H15 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX0P G15 Output
TX1N J13 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX1P H13 Output
4
DS280BR820
ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019
www.ti.com.cn
Copyright © 2016–2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
TX2N J11 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX2P H11 Output
TX3N J9 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX3P H9 Output
TX4N J7 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX4P H7 Output
TX5N J5 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX5P H5 Output
TX6N J3 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX6P H3 Output
TX7N H1 Output
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs.
TX7P G1 Output
CALIBRATION CLOCK PINS (FOR SUPPORTING UPGRADE PATH TO PIN-COMPATIBLE RETIMER DEVICE)
CAL_CLK_IN E1 Input
25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase
noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is
a need to support a future upgrade to the pin-compatible Retimer device. If there is no
need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is
not required. This input pin has a weak active pull-down and can be left floating if the
CAL_CLK feature is not required.
CAL_CLK_
OUT
E15 Output
2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a
daisy-chained fashion.
SYSTEM MANAGEMENT BUS (SMBus) PINS
ADDR0 D13 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on
power-up. The multi-level nature of these pins allows for 16 unique device addresses. The
four strap options include:
0: 1 kΩ to GND
R: 10 kΩ to GND
F: Float
1: 1 kΩ to VDD
ADDR1 E13 Input, 4-Level
ALL_DONE_
N
D3
Output,
LVCMOS
Indicates the completion of a valid EEPROM register load operation when in SMBus master
mode (EN_SMB = Float):
High = External EEPROM load failed or incomplete.
Low = External EEPROM load successful and complete.
When in SMBus slave mode (EN_SMB = 1 kΩ to VDD), this output will be high-Z until
READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. This behavior
allows the reset signal connected to READ_EN_N of one device to propagate to the
subsequent devices when ALL_DONE_N is connected to READ_EN_N in an SMBus slave
mode application.
EN_SMB E3 Input, 4-Level
4-level 2.5-V input used to select between SMBus master mode (float) and SMBus slave
mode (high). The four defined levels are:
0: 1 kΩ to GND - RESERVED
R: 10 kΩ to GND - RESERVED
F: Float - SMBus master mode
1: 1 kΩ to VDD - SMBus slave mode
READ_EN_N F13
Input,
LVCMOS
Pin has weak pull-up.
This pin is 3.3 V tolerant.
SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master
mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of
ALL_DONE_N low), this pin can be held low for normal device operation.
SMBus slave mode (EN_SMB = 1 kΩ to VDD): When asserted low, this causes the device to
be held in reset (SMBus state machine reset and register reset). This pin should be pulled
high or left floating for normal operation in SMBus slave mode.
SDA E12
I/O, 3.3-V
LVCMOS,
Open Drain
SMBus data input and open drain output. External 2-kΩ to 5-kΩ pull-up resistor is required.
This pin is 3.3-V LVCMOS tolerant.
5
DS280BR820
www.ti.com.cn
ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019
Copyright © 2016–2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
SDC F12
I/O, 3.3-V
LVCMOS,
Open Drain
SMBus clock input and open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is
required. This pin is 3.3-V LVCMOS tolerant.
MISCELLANEOUS PINS
INT_N F3 No Connect
No connect on package. For applications using multiple repeaters and retimers, this pin
should be connected to other devices’ INT_N pins. This is only a recommendation for cases
where there is a need to support a potential future upgrade to the pin-compatible retimer
device, which uses this pin as an interrupt signal to a system controller.
TEST0 E2
Input,
LVCMOS
Reserved test pin. During normal (non-test-mode) operation, this pin is configured as an
input and therefore is not affected by the presence of a signal. This pin may be left floating,
tied to GND, or connected to a 2.5-V (max) output.
TEST1 E14
Input,
LVCMOS
POWER
GND
A1, A2, A4,
A6, A8, A10,
A12, A14,
A15, B2, B4,
B6, B8, B10,
B12, B14,
C2, C3, C4,
C5, C6, C7,
C8, C9, C10,
C11, C12,
C13, C14,
D1, D2, D4,
D5, D7, D9,
D11, D12,
D14, D15,
E4, E11, F1,
F2, F4, F5,
F7, F9, F11,
F14, F15,
G2, G3, G4,
G5, G6, G7,
G8, G9, G10,
G11, G12,
G13, G14,
H2, H4, H6,
H8, H10,
H12, H14, J1,
J2, J4, J6,
J8, J10, J12,
J14, J15
Power
Ground reference. The GND pins on this device should be connected through a low-
impedance path to the board GND plane.
VDD
D6, D8, D10,
E5, E6, E7,
E8, E9, E10,
F6, F8, F10
Power
Power supply, VDD = 2.5 V ±5%. Use at least six de-coupling capacitors between the
Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four
0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD
pins as possible. The VDD pins on this device should be connected through a low-resistance
path to the board VDD plane. For more information, see Power Supply Recommendations.
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