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BLOCK A CODEC

BLOCK B CODEC

SIX AUDIO INPUTS (SIX

SINGLE-ENDED OR

FOUR DIFFERENTIAL

OUTPUTS)

LEVEL CONTROL PER

INPUT

MIXER

TWO PGAs (ONE PGA

PER CHANNEL)

SIX AUDIO INPUTS (SIX

SINGLE-ENDED OR

FOUR DIFFERENTIAL

OUTPUTS)

LEVEL CONTROL PER

INPUT

MIXER

TWO PGAs (ONE PGA

PER CHANNEL)

MICBIAS

ADC

AUDIO SERIAL

DATA BUS A

PLL

AUDIO SERIAL

DATA BUS B

DAC

SEVEN AUDIO

OUTPUTS (SIX SINGLE-

ENDED OR THREE

DIFFERENTIAL

OUTPUTS)

LEVEL CONTROL PER

OUTPUT

MIXER

VOLUME CONTROL

SEVEN AUDIO

OUTPUTS (SIX SINGLE-

ENDED OR THREE

DIFFERENTIAL

OUTPUTS)

LEVEL CONTROL PER

OUTPUT

MIXER

VOLUME CONTROL

DAC

GPIO

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV320AIC34

SLAS538B –OCTOBER 2007–REVISED NOVEMBER 2016

TLV320AIC34 Four-Channel, Low-Power Audio Codec

for Portable Audio and Telephony

1 Features

• Four-Channel Audio DAC

– 102-dBA Signal-to-Noise Ratio

– 16-, 20-, 24-, and 32-Bit Data

– Supports Rates From 8 kHz to 96 kHz

– 3D, Bass, Treble, EQ, and De-Emphasis

Effects

– Flexible Power Saving Modes and

Performance Are Available

• Four-Channel Audio ADC

– 92-dBA Signal-to-Noise Ratio

– Supports Rates From 8 kHz to 96 kHz

– Digital Signal Processing and Noise Filtering

Available During Record

• Twelve Audio Inputs

– Programmable in Single-Ended or Fully

Differential Configurations

– 3-State Capability for Floating Input

Configurations

• Fourteen Audio Output Drivers

– Stereo 8-Ω, 500-mW/Channel Speaker Drive

Capability

– Multiple Fully Differential or Single-Ended

Headphone Drivers

– Multiple Fully Differential or Single-Ended Line

Outputs

– Fully Differential Mono Outputs

• Low Power: 15-mW Stereo 48-kHz Playback With

3.3-V Analog Supply

• Ultra-Low-Power Mode With Passive Analog

Bypass

• Programmable Input/Output Analog Gains

• Automatic Gain Control (AGC) for Record

• Programmable Microphone Bias Level

• Dual Programmable PLLs for Flexible Clock

Generation

• I

C Control Bus

• Dual Audio Serial Data Busses

– Support I

S, Left- or Right-Justified, DSP,

PCM, and TDM Modes

– Enable Asynchronous Simultaneous Operation

of Busses and Data Converters

• Digital Microphone Input Support

• Concurrent Digital Microphone and Analog

Microphone Support Available

• Extensive Modular Power Control

• Power Supplies:

– Analog: 2.7 V to 3.6 V

– Digital Core: 1.65 V to 1.95 V

– Digital I/O: 1.1 V to 3.6 V

• Package: 6-mm × 6-mm 87-pin NFBGA

2 Applications

• Digital Cameras

• Smart Cellular Phones

3 Description

The TLV320AIC34 device is a low-power four-

channel audio codec with four-channel headphone

amplifier, as well as multiple inputs and outputs

programmable in single-ended or fully differential

configurations. Extensive register-based power

control is included, enabling four-channel 48-kHz

DAC playback as low as 15 mW from a 3.3-V analog

supply, making it ideal for portable battery-powered

audio and telephony applications.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TLV320AIC34 NFBGA (87) 6.00 mm × 6.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Block A and B Codec

TLV320AIC34

SLAS538B –OCTOBER 2007–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: TLV320AIC34

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Device Comparison Table..................................... 3

7 Pin Configuration and Functions......................... 4

8 Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Electrical Characteristics........................................... 7

8.6 Timing Requirements.............................................. 10

8.7 Typical Characteristics............................................ 15

9 Detailed Description............................................ 17

9.1 Overview ................................................................. 17

9.2 Functional Block Diagram ....................................... 18

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 44

9.5 Programming........................................................... 48

9.6 Register Maps......................................................... 49

10 Application and Implementation........................ 87

10.1 Application Information.......................................... 87

10.2 Typical Application ................................................ 87

11 Power Supply Recommendations ..................... 91

12 Layout................................................................... 91

12.1 Layout Guidelines ................................................. 91

12.2 Layout Example .................................................... 92

13 Device and Documentation Support ................. 93

13.1 Documentation Support ........................................ 93

13.2 Receiving Notification of Documentation Updates 93

13.3 Related Links ........................................................ 93

13.4 Community Resources.......................................... 93

13.5 Trademarks........................................................... 93

13.6 Electrostatic Discharge Caution............................ 93

13.7 Glossary................................................................ 93

14 Mechanical, Packaging, and Orderable

Information ........................................................... 94

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2007) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet...................................... 1

• Deleted ZAS package information from pinout diagram in Pin Configurations and Functions section ................................. 4

• Deleted Lead temperature, maximum reflow temperature (60 s): 260°C............................................................................... 6

• Deleted Dissipation Ratings table........................................................................................................................................... 7

• Changed Thermal impedance, R

θJA

, value From: 47 To: 53.8............................................................................................... 7

TLV320AIC34

www.ti.com

SLAS538B –OCTOBER 2007–REVISED NOVEMBER 2016

Product Folder Links: TLV320AIC34

5 Description (continued)

The record path of the TLV320AIC34 contains integrated microphone bias, digitally controlled four-channel

microphone preamplifier, and automatic gain control (AGC), with mix or mux capability among the multiple

analog inputs. Programmable filters are available during record which can remove audible noise that can occur

during optical zooming in digital cameras. The playback path includes mix or mux capability from the four-

channel DAC and selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC34 contains eight high-power output drivers as well as six line-level output drivers. The high-

power output drivers are capable of driving a variety of load configurations, including up to eight channels of

single-ended 16-Ω headphones using ac-coupling capacitors, or four channels in a capless output configuration.

In addition, for codec A, pairs of drivers can be used to drive mono or stereo 8-Ω speakers directly in a BTL

configuration at 500 mW per channel.

The four-channel audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital

filtering in each path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz,

44.1-kHz, and 48-kHz rates. The four-channel audio ADC supports sampling rates from 8 kHz to 96 kHz and is

preceded by programmable gain amplifiers providing up to 59.5-dB analog gain for low-level microphone inputs.

The TLV320AIC34 provides an extremely high range of programmability for both attack (8 to 1,408 ms) and for

decay (0.05 to 22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of

applications.

For battery saving applications where neither analog nor digital signal processing is required, the device can be

put in a special analog signal pass-through mode. This mode significantly reduces power consumption, as most

of the device is powered down during this pass through operation.

The serial control bus supports normal-speed and fast I

C protocols, whereas the dual serial audio data busses

are programmable for I

S, left- or right-justified, DSP, PCM, or TDM mode. Two highly programmable PLLs are

included for flexible clock generation and support for all standard audio rates from a wide range of available

MCLK_x frequencies, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of

12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

The TLV320AIC34 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to 1.95 V,

and a digital I/O supply of 1.1 V to 3.6 V. The device is available in a 6-mm × 6-mm, 87-ball NFBGA package.

6 Device Comparison Table

FUNCTION TLV320AIC34 TLV320AIC3106 TLV320AIC3104 TLV320AIC3120

Number of DAC 4 2 2 1

Number of ADC 4 2 2 1

Input/Output 12/14 10/7 6/6 3/2

Resolution (Bit) 16, 20, 24, 32 16, 20, 24, 32 16, 20, 24, 32 16, 20, 24, 32

Control interface I

C I

C, SPI I

C I

Digital audio interface

LJ, RJ, I

TDM, DSP

LJ, RJ, I

TDM, DSP

LJ, RJ, I

TDM, DSP

LJ, RJ, I

TDM, DSP

Number of digital audio interfaces 2 1 1 1

Speaker amplifier type

Mono or Stereo

Speaker (BTL)

— — Mono Differential

Class-D

Configurable miniDSP No No No Yes

Headphone driver Yes Yes Yes Yes

1 2

6 7 8 9 10

P0061-01

TLV320AIC34

SLAS538B –OCTOBER 2007–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: TLV320AIC34

7 Pin Configuration and Functions

ZAS Package

87-Pin NFBGA

Top View

Pin Functions

I/O DESCRIPTION

NAME NO.

ADDR_A L7 I

C address control A

ADDR_B L8 I

C address control B

AVDD_DAC B3 — Analog DAC voltage supply, 2.7 V – 3.6 V

AVSS_ADC D8 — Analog ADC ground supply, 0 V

AVSS_DAC D4, E4, F4, G4 — Analog DAC ground supply, 0 V

BCLK_A K3 I/O Audio serial data bus bit clock (input/output) A

BCLK_B L2 I/O Audio serial data bus bit clock (input/output) B

DIN_A K5 I Audio serial data bus data input (input) A

DIN_B L4 I Audio serial data bus data input (input) B

DOUT_A K6 O Audio serial data bus data output (output) A

DOUT_B L5 O Audio serial data bus data output (output) B

DRVDD B4, A4 — ADC analog and output driver voltage supply, 2.7 V to 3.6 V

DRVDD B9, A9 — Analog ADC and output driver voltage supply, 2.7 V to 3.6 V

DRVSS D5, D6, D7 — Analog output driver ground supply, 0 V

DVDD K1 — Digital core voltage supply, 1.65 V to 1.95 V

DVSS

E8, F8, G8, H4,

H5, H6, H8

— Digital core / I/O ground supply, 0 V

GPIO1_A J2 I/O General-purpose input/output #1–A

GPIO1_B J1 I/O General-purpose input/output #1–B

GPIO2_A H2 I/O

General-purpose input/output #2 (input/output), digital microphone data input, PLL clock input, audio

serial data bus bit clock input/output–A

GPIO2_B H1 I/O

General-purpose input/output #2 (input/output), digital microphone data input, PLL clock input, audio

serial data bus bit clock input/output–B

HPLCOM_A B7 O High-power output driver (left minus or multifunctional) A, capable of driving 8-Ω load

HPLCOM_B A7 O High-power output driver (left minus or multifunctional) B

HPLOUT_A B8 O High-power output driver (left plus) A, capable of driving 8-Ω load

HPLOUT_B A8 O High-power output driver (left plus) B

HPRCOM_A B6 O High-power output driver (right minus or multifunctional) A, capable of driving 8-Ω load

HPRCOM_B A6 O High-power output driver (right minus or multifunctional) B

HPROUT_A B5 O High-power output driver (right plus) A, capable of driving 8-Ω load

HPROUT_B A5 O High-power output driver (right plus) B

TLV320AIC34

www.ti.com

SLAS538B –OCTOBER 2007–REVISED NOVEMBER 2016

Product Folder Links: TLV320AIC34

Pin Functions (continued)

I/O DESCRIPTION

NAME NO.

IOVDD H7, K7 — I/O voltage supply, 1.1 V to 3.6 V

LEFT_LOM_A D2 O Left line output (minus) A

LEFT_LOM_B D1 O Left line output (minus) B

LEFT_LOP_A C2 O Left line output (plus) A

LEFT_LOP_B C1 O Left line output (plus) B

LINE1LM_A L10 I MIC1 or Line1 analog input (left minus or multifunction) A

LINE1LM_B L11 I MIC1 or Line1 analog input (left minus or multifunction) B

LINE1LP_A K9 I MIC1 or Line1 analog input (left plus or multifunction) A

LINE1LP_B K8 I MIC1 or Line1 analog input (left plus or multifunction) B

LINE1RM_A J10 I MIC1 or Line1 analog input (right minus or multifunction) A

LINE1RM_B J11 I MIC1 or Line1 analog input (right minus or multifunction) B

LINE1RP_A K10 I MIC1 or Line1 analog input (right plus or multifunction) A

LINE1RP_B K11 I MIC1 or Line1 analog input (right plus or multifunction) B

LINE2LM_A G10 I MIC2 or Line2 analog input (left minus or multifunction) A

LINE2LM_B G11 I MIC2 or Line2 analog input (left minus or multifunction) B

LINE2LP_A H10 I MIC2 or Line2 analog input (left plus or multifunction) A

LINE2LP_B H11 I MIC2 or Line2 analog input (left plus or multifunction) B

LINE2RM_A E10 I MIC2 or Line2 analog input (right minus or multifunction) A

LINE2RM_B E11 I MIC2 or Line2 analog input (right minus or multifunction) B

LINE2RP_A F10 I MIC2 or Line2 analog input (right plus or multifunction) A

LINE2RP_B F11 I MIC2 or Line2 analog input (right plus or multifunction) B

MCLK_A K2 I Master clock input A

MCLK_B L1 I Master clock input B

MIC3L_A D10 I MIC3 input (left or multifunction) A

MIC3L_B D11 I MIC3 input (left or multifunction) B

MIC3R_A A10 I Microphone or line input 3 right A

MIC3R_B A11 I Microphone or line input 3 right B

MICBIAS_A B10 O Microphone bias voltage output A

MICBIAS_B B11 O Microphone bias voltage output B

MICDET_A C10 I Microphone detect A

MICDET_B C11 I Microphone detect B

MONO_LOM_A A2 O Mono line output (minus) A

MONO_LOM_B B1 O Mono line output (minus) B

MONO_LOP_A A3 O Mono line output (plus) A

MONO_LOP_B A1 O Mono line output (plus) B

RESET_A G2 I Reset A

RESET_B G1 I Reset B

RIGHT_LOM_A F2 O Right line output (minus) A

RIGHT_LOM_B F1 O Right line output (minus) B

RIGHT_LOP_A E2 O Right line output (plus) A

RIGHT_LOP_B E1 O Right line output (plus) B

SCL L9 I/O

C serial clock

SDA L6 I/O

C serial data input/output

WCLK_A K4 I/O Audio serial data bus word clock (input/output) A

WCLK_B L3 I/O Audio serial data bus word clock (input/output) B

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