没有合适的资源?快使用搜索试试~ 我知道了~
TI-TLV320AIC3263.pdf
需积分: 5 0 下载量 158 浏览量
2022-12-03
23:43:21
上传
评论 4
收藏 1.55MB PDF 举报
温馨提示
试读
64页
TI-TLV320AIC3263.pdf
资源推荐
资源详情
资源评论
TLV320AIC3263
www.ti.com
SLAS923 –JUNE 2013
Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Class-D
Speaker Amplifier
Check for Samples: TLV320AIC3263
1
FEATURES
• Three Independent Digital Audio Serial
Interfaces with Separate I/O Power Voltages
2
• Stereo Audio DAC with 101dB SNR
– TDM and mono PCM support on all Audio
• 2.7mW Stereo 48kHz DAC Playback
Serial Interfaces
• Stereo Audio ADC with 93dB SNR
– 8-channel Input and Output on Audio Serial
• 6.1mW Stereo 48kHz ADC Record
Interface 1
• 8-192kHz Playback and Record
• Programmable PLL, plus Low-Frequency
• 30mW DirectPath
TM
Headphone Driver
Clocking
Eliminates Large Output DC-Blocking
• Programmable 12-Bit SAR ADC
Capacitors
• SPI and I
2
C Control Interfaces
• 128mW Differential Receiver Output Driver
• 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP
• Class-D Speaker Driver
(DSBGA) Package
– 1.7 W (8Ω , 5.5V, 10% THDN)
AIC3262
– 1.4 W (8Ω , 5.5V, 1% THDN)
APPLICATIONS
• Stereo Line Outputs
• Mobile Handsets
• PowerTune™ - Adjusts Power versus SNR
• Tablets, eBooks
• Extensive Signal Processing Options
• Portable Navigation Devices (PND)
• Eight Single-Ended or 4 Fully-Differential
• Portable Media Player (PMP)
Analog Inputs
• Portable Gaming Systems
• Analog Microphone Inputs, and Up to 4
• Portable Computing
Simultaneous Digital Microphone Channels
• Active Noise Cancellation (ANC)
• Low Power Analog Bypass Mode
• Speaker Protection
• Fully-programmable Enhanced miniDSP with
• Advanced DSP algorithms
PurePath
TM
Studio Support
– Extensive Algorithm Support for Voice and
Audio Applications
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerTune is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SPI_SELECT
IN1R/AUX2
IN2R
IN3R
IN3L
IN4L
IN2L
IN1L/AUX1
DRCAGC
DRC
t
PR
t
PL
AGC
Audio
Interface
Ref
MICBIAS
VREF_AUDIO
LOL
LOR
–36...0dB
–36...0dB
CPVDD_18
CPVSS
CPFCP
CPFCM
VNEG
MICBIAS_EXT
PLL
GPO1
I2C_ADDR_
SCLK
DIN3
GPIO1
GPIO2
DOUT3
DOUT2
WCLK2
BCLK2
WCLK1
BCLK1
VBAT
VREF_SAR
+
+
–
–
–12, –6, 0dB
–12, –6, 0dB
WCLK3
BCLK3
MICDET Detection
Mic
Bias Charge
Pump
Primary
Audio Interface
Secondary
Audio IF
Interrupt
Ctrl
Digital
Mic. (x4)
SPI / I C
Control Block
2
Low Freq
Clocking
-12, -6, 0dB
)
ADC
Signal
Proc.
DAC
Signal
Proc.
DAC
Signal
Proc.
ADC
Signal
Proc.
miniDSP
ASRC
Dig Mixer
Volume
miniDSP
Dig Mixer
Volume
Right
ADC
Left
ADC
SAR
ADC
Right
DAC
Left
DAC
0=47.5dB
(0.5-dB Steps)
0=47.5dB
(0.5-dB Steps)
)
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
–6 dB
GPIO6
MCLK
GPIO5
DOUT1
Tertiary
Audio IF
IN4R
–6 dB
Supplies
IOVDD1
RECVDD_33
AVDD1_18
AVDD2_18
SPK_V
MICBIAS_VDD
AVDD_18
AVDD4_18
DVDD
RECVSS
SVDD
HVDD_18
SVSS
IOVSS
AVSS1
AVSS2
AVSS3
AVSS
DVSS
AVSS4
LOL
-78...0dB
MAL
MAR
-6dB
-6dB
LOL
-78...0dB
-78...0dB
-78...0dB
-78...0dB
RECP
RECM
-6...29dB
(1-dB Steps
-6...14dB
(1-dB Steps
HPL
HPR
-78...0dB
-78...0dB
HPVSS_SENSE
6...30dB
SPKM
SPKP
(6-dB Steps)
)
-6...14dB
(1-dB Steps
-12, -6, 0dB
TEMP
VBAT
IN1R/AUX2
IN1L/AUX1
TEMP
SENSOR
GPIO3
GPIO4
SCL
SDA
RESET
Vol. Ctrl.
LOR
Pin Muxing / Clock Routing
IN1L
IN1R
Vol. Ctrl.
Int.
Ref.
in Adj.Ga
in Adj.
Ga
DIN1
DIN2
IOVDD2
IOVDD3
LOR
-78...0dB
RIGHT_
CH_IN
TLV320AIC3263
SLAS923 –JUNE 2013
www.ti.com
DESCRIPTION
The TLV320AIC3263 (also referred to as the AIC3263) is a flexible, highly-integrated, low-power, low-voltage
stereo audio codec. The AIC3263 features four digital microphone inputs, plus programmable outputs,
PowerTune capabilities, enhanced fully-programmable miniDSP, predefined and parameterizable signal
processing blocks, integrated PLL, and flexible digital audio interfaces. Extensive register-based control of power,
input and output channel configuration, gains, effects, pin-multiplexing and clocks are included, allowing the
device to be precisely targeted to its application.
Figure 1. Simplified Block Diagram
2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3263
TLV320AIC3263
www.ti.com
SLAS923 –JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3263 features two fully-programmable miniDSP cores that support application-specific algorithms
in the record and/or the playback path of the device. The miniDSP cores are fully software programmable.
Targeted miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP
filtering are loaded into the device after power-up.
Combined with the advanced PowerTune technology, the device can execute operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3263 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations which cover single-ended and differential setups, as well as
floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise
that may be introduced by mechanical coupling, such as optical zooming in a digital camera. The record path can
also be configured for up to two stereo (such as up to 4) simultaneous digital microphone Pulse Density
Modulation (PDM) interfaces typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D
speaker output; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The
playback path contains two high-power DirectPath
TM
headphone output drivers which eliminate the need for ac
coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone
drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In
addition, playback audio can be routed to an integrated Class-D speaker driver or a differential receiver amplifier.
The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-
off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used
in a mobile environment. When used in a docked environment power consumption typically is less of a concern
while lowest possible noise is important. With PowerTune the TLV320AIC3263 can address both cases.
The required internal clock of the TLV320AIC3263 can be derived from multiple sources, including the MCLK pin,
the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal PLL, where the
input to the PLL again can be derived from similar pins. Although using the internal fractional PLL ensures the
availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly
programmable and can accept available input clocks in the range of 512kHz to 50MHz. To enable even lower
clock frequencies, an integrated low-frequency clock multiplier can also be used as an input to the PLL.
The TLV320AIC3263 has a 12-bit SAR ADC converter that supports system voltage measurements. These
system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or
VBAT pins), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
The device also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF, LJF, and
mono PCM formats. This enables three simultaneous digital playback and record paths to three independent
digital audio buses or chips. Additionally, the general purpose interrupt pins can be used to connect to a fourth
digital audio bus, allowing the end system to easily switch in this fourth audio bus to one of the three Digital
Audio Serial Interfaces. Each of the three Digital Audio Serial Interfaces can be run using separate power
voltages to enable easy integration with separate chips with different I/O voltages.
The device is available in the 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP (DSBGA) Package.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TLV320AIC3263
J
H
G
F
E
D
C
B
A CPFCM VNEG
1
23456
789
WCSP Package
(Top View)
CPVDD
_18
AVSS4SPKP
SVSS
CPFCP
CPVSS
HPL
HVDD
_18
RECM
RECP MICDET
IN4L
AVDD 1
_18
MICBIAS
_EXT
MICBIAS
AVDD 2
_18
LOL
AVDD 4
_18
SPKM
VREF_
AUDIO
VREF_
SAR
IN1L/
AUX1
IN1R/
AUX2
IN4R
HPVSS_
SENSE
LOR
GPIO4
IN3RIN3LAVSS
AVSS 1AVSS 3AVSS 2
DVSS
SPK_V
DVSS
IN2LIN2R
AVDD
_18
DVSS
GPIO5
GPO1
GPIO3
IOVSS
VBAT
MCLKBCLK2
DIN2
WCLK2 WCLK3
DIN3
SPI_
SELECT
RESET
BCLK 1
DOUT 1IOVDD 1SCL
SDA
IOVDD 3
BCLK3
GPIO 2
IOVDD2
DIN1
WCLK1DVDDIOVSS
DVSS
DOUT2
DOUT 3
GPIO1
DVDD
HPR
RECVDD
_33
RECVSS
MICBIAS
_VDD
SVDD
GPIO 6
I2C_
ADDR _
SCLK
DVDD
TLV320AIC3263
SLAS923 –JUNE 2013
www.ti.com
Package and Signal Descriptions
Packaging/Ordering Information
OPERATING
PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT
(1)
PACKAGE TEMPERATURE
DESIGNATOR NUMBER QUANTITY
RANGE
TLV320AIC3263 I YZFT Tape and Reel, 250
WCSP-81
TLV320AIC3263 YZF –40°C to 85°C
(DSBGA)
TLV320AIC3263 I YZFR Tape and Reel, 3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Pin Assignments
space
space
Figure 2. WCSP-81 (DSBGA) (YZF) Package Ball Assignments, Top View
4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3263
TLV320AIC3263
www.ti.com
SLAS923 –JUNE 2013
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package
WCSP (YZF)
POWER
BALL NAME I/O/P DESCRIPTION
DOMAIN
LOCATION
A1 MICBIAS_VDD P Analog Power Supply for Micbias
A2 RECVSS P Analog Receiver Driver Ground
A3 RECVDD_33 P Analog 3.3V Power Supply for Receiver Driver
A4 HPR O Analog Right Headphone Output
A5 VNEG I/O Analog Charge Pump Negative Supply
A6 CPFCM I/O Analog Charge Pump Flying Capacitor M terminal
A7 CPVDD_18 P Analog Power Supply Input for Charge Pump
A8 AVSS4 P Analog Analog Ground for Class-D
A9 SPKP O Speaker Left Channel P side Class-D Output
B1 MICDET I/O Analog Headset Detection Pin
B2 RECP O Analog Receiver Driver P side Output
B3 RECM O Analog Receiver Driver M side Output
B4 HVDD_18 P Analog Headphone Amp Power Supply
B5 HPL O Analog Left Headphone Output
B6 CPVSS P Analog Charge Pump Ground
B7 CPFCP I/O Analog Charge Pump Flying Capacitor P Terminal
B8 SVDD P Speaker Class-D Output Stage Power Supply
B9 SVSS P Speaker Class-D Output Stage Ground
C1 IN4L I Analog Analog Input 4 Left
C2 AVDD1_18 P Analog 1.8V Analog Power Supply
C3 MICBIAS_EXT O Analog Output Bias Voltage for Headset Microphone.
C4 MICBIAS O Analog Output Bias Voltage for Microphone to be used for on-board Microphones
C5 AVDD2_18 P Analog 1.8V Analog Power Supply
C6 LOL O Analog Left Line Output
C7 AVDD4_18 P Analog 1.8V Analog Power Supply for Class-D
C8 SPKM O Speaker M side Class-D Output
C9 SPK_V P Speaker Class-D Output Stage Power Supply (Connect to SVDD through a Resistor)
D1 VREF_AUDIO O Analog Analog Reference Filter Output
SAR ADC Voltage Reference Input or Internal SAR ADC Voltage Reference
D2 VREF_SAR I/O Analog
Bypass Capacitor Pin
Analog Input 1 Left, Auxiliary 1 Input to SAR ADC
D3 IN1L/AUX1 I Analog (Special Function: Left Channel High Impedance Input for Capacitive Sensor
Measurement)
Analog Input 1 Right, Auxiliary 2 Input to SAR ADC
D4 IN1R/AUX2 I Analog (Special Function: Right Channel High Impedance Input for Capacitive
Sensor Measurement)
D5 IN4R I Analog Analog Input 4 Right
D6 HPVSS_SENSE I Analog Headphone Ground Sense Terminal
D7 LOR O Analog Right Line Output
D8 VBAT I Speaker Battery Monitor Voltage Input
D9 DVSS P Digital Digital Ground
E1 IN3R I Analog Analog Input 3 Right
E2 IN3L I Analog Analog Input 3 Left
E3 AVSS P Analog Analog Ground
E4 AVSS1 P Analog Analog Ground
E5 AVSS3 P Analog Analog Ground
E6 AVSS2 P Analog Analog Ground
E7 DVDD P Digital 1.8V Digital Power Supply
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TLV320AIC3263
剩余63页未读,继续阅读
资源评论
不觉明了
- 粉丝: 3188
- 资源: 5486
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功