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TI-TLV320AIC3105.pdf
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TLV320AIC3105
SLAS513C –FEBRUARY 2007–REVISED DECEMBER 2014
TLV320AIC3105 Low-Power Stereo Audio Codec for Portable Audio and Telephony
1 Features 3 Description
The TLV320AIC3105 is a low-power stereo audio
1
• Stereo Audio DAC
codec with multiple single-ended inputs and a stereo
– 102-dBA Signal-to-Noise Ratio
headphone amplifier. The output stages are
– 16/20/24/32-Bit Data
programmable in single-ended or fully differential
configurations. Extensive register-based power
– Supports Rates From 8 kHz to 96 kHz
control is included, enabling stereo 48-kHz DAC
– 3D/Bass/Treble/EQ/De-Emphasis Effects
playback as low as 14 mW from a 3.3-V analog
– Flexible Power Saving Modes and
supply, making it ideal for portable battery-powered
Performance are Available
audio and telephony applications.
• Stereo Audio ADC
The record path of the TLV320AIC3105 contains
– 92-dBA Signal-to-Noise Ratio
integrated microphone bias, digitally controlled stereo
microphone preamplifier, and automatic gain control
– Supports Rates From 8 kHz to 96 kHz
(AGC), with mix/mux capability among the multiple
– Digital Signal Processing and Noise Filtering
analog inputs. Programmable filters are available
Available During Record
during record which can remove audible noise that
• Six Audio Input Pins
can occur during optical zooming in digital cameras.
The playback path includes mix/mux capability from
– Six Stereo Single-Ended Inputs
the stereo DAC and selected inputs, through
• Six Audio Output Drivers
programmable volume controls, to the various
– Stereo Fully Differential or Single-Ended
outputs.
Headphone Drivers
Device Information
(1)
– Fully Differential Stereo Line Outputs
PART NUMBER PACKAGE BODY SIZE (NOM)
• Low Power: 14-mW Stereo 48-kHz Playback With
TLV320AIC3105 VQFN (32) 5.00 mm × 5.00 mm
3.3-V Analog Supply
(1) For all available packages, see the orderable addendum at
• Ultralow-Power Mode with Passive Analog Bypass
the end of the datasheet.
• Programmable Input/Output Analog Gains
• Automatic Gain Control (AGC) for Record
Simplified Diagram
• Programmable Microphone Bias Level
• Programmable PLL for Flexible Clock Generation
• I
2
C Control Bus
• Audio Serial Data Bus Supports I
2
S, Left/Right-
Justified, DSP, and TDM Modes
• Extensive Modular Power Control
• Power Supplies:
– Analog: 2.7 V–3.6 V.
– Digital Core: 1.525 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
• Package: 5-mm × 5-mm 32-Pin VQFN
2 Applications
• Digital Cameras
• Smart Cellular Phones
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3105
SLAS513C –FEBRUARY 2007–REVISED DECEMBER 2014
www.ti.com
Table of Contents
10.2 Functional Block Diagram ..................................... 18
1 Features.................................................................. 1
10.3 Feature Description............................................... 19
2 Applications ........................................................... 1
10.4 Device Functional Modes...................................... 40
3 Description ............................................................. 1
10.5 Programming......................................................... 42
4 Revision History..................................................... 2
10.6 Register Maps ...................................................... 46
5 Description (Continued)........................................ 3
11 Application and Implementation........................ 90
6 Related Devices ..................................................... 4
11.1 Application Information.......................................... 90
7 Pin Configuration and Functions......................... 4
11.2 Typical Applications .............................................. 90
8 Specifications......................................................... 6
12 Power Supply Recommendations ..................... 93
8.1 Absolute Maximum Ratings ...................................... 6
13 Layout................................................................... 93
8.2 ESD Ratings ............................................................ 6
13.1 Layout Guidelines ................................................. 93
8.3 Recommended Operating Conditions....................... 7
13.2 Layout Example .................................................... 94
8.4 Thermal Information.................................................. 7
14 Device and Documentation Support ................. 95
8.5 Electrical Characteristics........................................... 8
14.1 Trademarks........................................................... 95
8.6 Audio Data Serial Interface Timing Requirements . 11
14.2 Electrostatic Discharge Caution............................ 95
8.7 Typical Characteristics............................................ 15
14.3 Glossary................................................................ 95
9 Parameter Measurement Information ................ 17
15 Mechanical, Packaging, and Orderable
10 Detailed Description ........................................... 17
Information ........................................................... 95
10.1 Overview ............................................................... 17
4 Revision History
Changes from Revision B (December 2008) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
2 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3105
TLV320AIC3105
www.ti.com
SLAS513C –FEBRUARY 2007–REVISED DECEMBER 2014
5 Description (Continued)
The TLV320AIC3105 contains four high-power output drivers as well as two fully differential output drivers. The
high-power output drivers are capable of driving a variety of load configurations, including up to four channels of
single-ended 16-Ω headphones using ac-coupling capacitors, or stereo 16-Ω headphones in a capacitorless
output configuration.
The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering
in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-
kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by
programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone
inputs. The TLV320AIC3105 provides an extremely high range of programmability for both attack (8–1,408 ms)
and for decay (0.05–22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of
applications.
For battery saving applications where neither analog nor digital signal processing are required, the device can be
put in a special analog signal passthrough mode. This mode significantly reduces power consumption, as most of
the device is powered down during this passthrough operation.
The serial control bus supports the I2C protocol, while the serial audio data bus is programmable for I2S,
left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and
support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with
special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system
clocks.
The TLV320AIC3105 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.525 V–1.95 V,
and a digital I/O supply of 1.1 V–3.6 V. The device is available in a 5-mm × 5-mm 32-pin QFN package.
Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TLV320AIC3105
P0048-02
SDADVDD
DRVDD
MCLK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
32
10
31
11
30
12
29
13
28
1427
1526
1625
MIC1L/LINE1L
BCLK
MIC1R/LINE1R
WCLK
MIC2L/LINE2L
DIN
MIC2R/LINE2R
DOUT
MIC3L/LINE3L/MICDET
DVSS
MICBIAS
IOVDD
MIC3R/LINE3R
SCL
RHBPACKAGE
(BOTTOMVIEW)
RESET
HPROUT
RIGHT_LOM
HPRCOM
RIGHT_LOP
DRVSS
LEFT_LOM
HPLCOM
LEFT_LOP
HPLOUT
AVSS2
DRVDD
AVDD
AVSS1
TLV320AIC3105
SLAS513C –FEBRUARY 2007–REVISED DECEMBER 2014
www.ti.com
6 Related Devices
DEVICE NAME DESCRIPTION
TLV320AIC3105 Low-Power Stereo CODEC with 6 SE inputs, 6 outputs, HP Amp and Enhanced Digital Effects
TLV320AIC3101 Same as TLV320AIC3105, but with differential and SE inputs and Speaker/HP Amp
TLV320AIC3104 Same as TLV320AIC3105, but with differential and SE inputs.
TLV320AIC3106 Same as TLV320AIC3105, but with 10 differential and SE inputs and 7 outputs.
Same as TLV320AIC3105, but with 7 differential and SE inputs, 6 outputs and Integrated Mono
TLV320AIC3107
Class-D Amplifier
7 Pin Configuration and Functions
Connet device thermal pad to DRVSS.
4 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3105
TLV320AIC3105
www.ti.com
SLAS513C –FEBRUARY 2007–REVISED DECEMBER 2014
Pin Functions
PIN
I/O DESCRIPTION
NAME QFN NO.
AVDD 25 I Analog DAC voltage supply, 2.7 V–3.6 V
AVSS1 17 I Analog ADC ground supply, 0 V
AVSS2 26 I Analog DAC ground supply, 0 V
BCLK 2 I/O Audio serial data bus bit clock input/output
DIN 4 I Audio serial data bus data input
DOUT 5 O Audio serial data bus data output
DRVDD 18 O Analog ADC and output driver voltage supply, 2.7 V–3.6 V
DRVDD 24 O Analog output driver voltage supply, 2.7 V–3.6 V
DRVSS 21 O Analog output driver ground supply, 0 V
DVDD 32 I Digital core voltage supply, 1.525 V–1.95 V
DVSS 6 I/O Digital core / I/O ground supply, 0 V
HPLCOM 20 O High-power output driver (left – or multi-functional)
HPLOUT 19 O High-power output driver (left +)
HPRCOM 22 O High-power output driver (right – or multi-functional)
HPROUT 23 O High-power output driver (right +)
IOVDD 7 I/O Digital I/O voltage supply, 1.1 V–3.6 V
LEFT_LOM 28 O Left line output (–)
LEFT_LOP 27 O Left line output (+)
MCLK 1 I Master clock input
MIC1L/LINE1L 10 I Left input 1
MIC1R/LINE1R 11 I Right input 1
MIC2L/LINE2L 12 I Left input 2
MIC2R/LINE2R 13 I Right input 2
MIC3L/LINE3L/MICDET 14 I Left input 3; can support microphone detection
MIC3R/LINE3R 16 I Right input 3
MICBIAS 15 O Microphone bias voltage output
RESET 31 Reset
RIGHT_LOM 30 O Right line output (–)
RIGHT_LOP 29 O Right line output (+)
SCL 8 I/O I2C serial clock input
SDA 9 I/O I2C serial data input/output
WCLK 3 I/O Audio serial data bus word clock input/output
Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TLV320AIC3105
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