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TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-Bit Resolution, 35 MSPS Sampling

Analog-to-Digital Converter (ADC)

Low Power Consumption: 90 mW Typ

Using External References

Wide Analog Input Bandwidth: 600 MHz Typ

3.3-V Single-Supply Operation

3.3-V TTL/CMOS-Compatible Digital I/O

Internal Bottom and Top Reference

Voltages

Adjustable Reference Input Range

Power-Down (Standby) Mode

Separate Power Down for Internal Voltage

References

Three-State Outputs

28-Pin Thin Shrink SOP (TSSOP) Packages

Applications

– Digital Communications (IF Sampling)

– High-Speed DSP Front-End

(TMS320C6000)

– Medical Imaging

– Video Processing (Scan Rate/Format

Conversion)

– DVD Read Channel Digitization

description

The TLV5535 is an 8-bit, 35 MSPS, high-speed A/D converter. It converts the analog input signal into 8-bit

binary-coded digital words up to a sampling rate of 35 MHz. All digital inputs and outputs are 3.3 V

TTL/CMOS-compatible.

The device consumes very little power due to the 3.3-V supply and an innovative single-pipeline architecture

implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage

references from user-supplied voltages. If no external references are available, on-chip references are

available for internal and external use. The full-scale range is 1 V

up to 1.6 V

, depending on the analog

supply voltage. If external references are available, the internal references can be disabled independently from

the rest of the chip, resulting in an even greater power saving.

While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed

graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD

read channel digitization, medical imaging, and communications. This device is suitable for IF sampling of

communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.

AVAILABLE OPTIONS

PACKAGED DEVICES

TSSOP-28

–40°C to 85°C TLV5535IPW

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DRV

CLK

AIN

CML

PWDN_REF

REFBO

REFBI

REFTI

REFTO

STBY

PW PACKAGE

(TOP VIEW)

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AIN 26 I Analog input

16, 27 I Analog supply voltage

18, 23, 28 I Analog ground

BG 17 O Band gap reference voltage. A 1-µF capacitor (with an optional 0.1-µF capacitor in parallel) should be

connected between this terminal and AV

for external filtering.

CLK 12 I Clock input. The input is sampled on each rising edge of CLK.

CML 25 O Common mode level. This voltage is equal to (AV

– AV

) ÷ 2. An external 0.1-µF capacitor should be

connected between this terminal and AV

D0 – D7 2 – 9 O Data outputs. D7 is the MSB.

DRV

1 I Supply voltage for digital output drivers

DRV

10 I Ground for digital output drivers

14 I Digital supply voltage

OE 13 I Output enable. When high, the D0 – D7 outputs go in high-impedance mode.

11 I Digital ground

PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal disables the internal reference circuit.

REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the

ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering

should be applied to this input. The use of a 0.1-µF capacitor connected between REFBI and AV

recommended. Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be

connected to REFBI or left unconnected. A 1-µF capacitor between REFBO and AV

provides sufficient

decoupling required for this output.

REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.

It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be

applied to this input. The use of a 0.1-µF capacitor between REFTI and AV

is recommended.

Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be

connected to REFTI or left unconnected. A 1-µF capacitor between REFTO and AV

provides sufficient

decoupling required for this output.

STBY 15 I Standby input. A high level on this input enables power-down mode.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range: AV

to AV

, DV

to DV

–0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

to DV

, AV

to DV

–0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to DV

–0.5 V to DV

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AV

–0.5 V to AV

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range applied from external source to DGND –0.5 V to DV

+ 0.5 V. . . . . . . . . . . . . .

Reference voltage input range to AGND: V

(REFTI)

, V

(REFTO)

, V

(REFBI)

, V

(REFBO)

–0.5 V to AV

+ 0.5 V

Operating free-air temperature range, T

: TLV5535I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage

= DV

= DRV

= 3 V at I

= 50 µA,

Digital output forced high

2.8 V

Low-level output voltage

= DV

= DRV

= 3.6 V at I

= 50 µA,

Digital output forced low

0.1 V

Output capacitance 5 pF

OZH

High-impedance state output current to

high level

=DV

=DRV

=36V

10 µA

OZL

High-impedance state output current to

low level

DRV

10 µA

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Integral nonlinearity (INL) best fit

Internal references (see Note 1)

= 25°C –1.5 ±0.7 1.5 LSB

Integral

nonlinearit

(INL)

best

fit

Internal

references

(see

Note

= –40°C to 85°C –2.4 ±0.7 2.4 LSB

Differential nonlinearity (DNL) Internal references (see Note 2), T

= –40°C to 85°C –1 ±0.6 1.3 LSB

Zero error

= DV

= 3.3 V, DRV

= 3 V,

5 %FS

Full-scale error

DD DD DD

Internal references (see Note 3)

5 %FS

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under

test [i.e., (last transition level – first transition level) ÷ (2

– 2)]. Using this definition for DNL separates the effects of gain and offset

error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the

bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by

the number of ADC output levels (256).

Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches

the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5

LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references

divided by the number of ADC output levels (256).

analog input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input capacitance 4 pF

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