TI-TLV990-28.pdf资源-CSDN文库

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SLAS300A − AUGUST 2000 − REVISED MARCH 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D Single-Chip CCD Analog Front-End

D 10-Bit, 28-MSPS, Single 3-V Supply

Operation A/D Converter

D Very Low Power: 150-mW Typical, 2-mW

Power-Down Mode

D Differential Nonlinearity Error:

< ±0.5 LSB Typical

D Integral Nonlinearity Error:

< ±0.75 LSB Typical

D Programmable Gain Amplifier (PGA) With

0-dB to 36-dB Gain Range (0.045 dB/Step)

D Automatic or Programmable Optical Black

Level and Offset Calibration With Digital

Filter and Bad Pixel Limits

D Additional DACs for External Analog

Setting

D Serial Interface for Register Configuration

D Internal-Reference Voltages

D 48-Pin TQFP Package

application

D Digital Still Camera

D Video Camcorder

description

The TLV990-28 is a complete CCD signal

processor/digitizer designed for digital still

camera and PC camera applications. The

TLV990-28 performs all the analog-processing

functions necessary to maximize the dynamic range, corrects various errors associated with the CCD sensor,

and then digitizes the results with an on-chip high-speed analog-to-digital converter (ADC).

The key components of the TLV990-28 include: an input clamp circuit for CCD signal, a correlated double

sampler (CDS), a programmable-gain amplifier (PGA) with 0 to 36-dB gain range, two internal digital-to-analog

converters (DAC) for automatic or programmable optical black level and offset calibration, a 10-bit, 28-MSPS

pipeline ADC, a parallel data port for easy microprocessor interface, a serial port for configuring internal control

registers, two additional DACs for external system control, and internal reference voltages.

Designed in advanced CMOS process, the TLV990-28 operates from a single 3-V power supply with a normal

power consumption of 150 mW at 28 MSPS and 2 mW in power-down mode.

Its very high throughput rate, single 3-V operation, very low-power consumption, and fully-integrated

analog-processing circuitry make the TLV990-28 an ideal CCD signal-processing solution for digital still

cameras and electronic video camcorder applications.

This device is available in a 48-pin TQFP package and is specified over a –20°C to 75°C operating-temperature

range.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCKP

DACO

AGND

DD3

DIGND

DIV

AGND5

RBD

RMD

RPD

DD5

DD1

AGND1

CLCCD

CLREF

567 8

RESET

SDIN

SCLK

35 34 33 32 3136 30

BLKG

AGND4

DD2

28 27 2629

9 10 11 12

ADCCLK

OBCLP

STBY

CCDIN

AGND2

PFB PACKAGE

(TOP VIEW)

DGND

DD4

TLV990−28PFB



       

SLAS300A − AUGUST 2000 − REVISED MARCH 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL I/O DESCRIPTION

NAME NO.

ADCCLK 25 I ADC clock input

AGND1 44 Analog ground for internal CDS circuits

AGND2 4 Analog ground for internal PGA circuits

AGND3 20 Analog ground for internal DAC circuits

AGND4 32 Analog ground for internal ADC circuits

AGND5 37 Analog ground for internal REF circuits

DD1

43 Analog supply voltage for internal CDS circuits, 3 V

DD2

3 Analog supply voltage for internal PGA circuits, 3 V

DD3

19 Analog supply voltage for internal DAC circuits, 3 V

DD4

33 Analog supply voltage for internal ADC circuits, 3 V

DD5

41 Analog supply voltage for internal ADC circuits, 3 V

BLKG 36 I Control input. The CDS operation is disabled when BLKG is pulled low.

CLCCD 47 I CCD signal clamp control input

CCDIN 1 I CCD input

CLREF 48 O Clamp-reference-voltage output

CP 34, 35 I Connect these pins to AV

CS 28 I Chip select. A logic low on this input enables the serial port.

D0 – D9 7–16 O 10-bit 3-state ADC output data or offset DACs test data

DACO1 21 O Digital-to-analog converter output1

DACO2 22 O Digital-to-analog converter output2

DGND 5 Digital ground

DIGND 18 Digital-interface-circuit ground

DIV

17 Digital-interface-circuit supply voltage, 1.8 V− 4.4 V

6 Digital-supply voltage, 3 V

NC 2 I No connect

OBCLP 31 I Optical black-level and offset-calibration control input, active low

OE 24 I Output-data enable, active low

RBD 38 O Internal bandgap reference for external decoupling

RESET 29 I Hardware-reset input, active low. This signal forces a reset of all internal registers.

RMD 39 O Ref− output for external decoupling

RPD 40 O Ref+ output for external decoupling

SDIN 27 I Serial-data input to configure the internal registers

SCKP 23 I This pin selects the polarity of SCLK. 0 – active low (high when SCLK is not running), 1 – active high (low

when SCLK is not running).

SCLK 26 I Serial-clock input. This clock synchronizes the serial data transfer.

SR 45 I CCD reference-level-sample clock input

STBY 30 I Hardware power-down control input, active low

SV 46 I CCD signal-level sample clock input

42 Silicon substrate, normally connected to analog ground



       

SLAS300A − AUGUST 2000 − REVISED MARCH 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, AV

, DV

, DIV

−0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range −0.3 V to AV

+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range −0.3 V to DV

+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating

virtual junction temperature range, T

−40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

−20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN NOM MAX UNIT

Analog supply voltage AV

2.7 3 3.3 V

Digital supply voltage DV

2.7 3 3.3 V

Digital interface supply voltage DIV

1.8 4.4 V

digital inputs, DIV

= 3 V

MIN NOM MAX UNIT

High-level input voltage, V

0.8DIV

Low-level input voltage, V

0.2DIV

Input ADCCLK frequency 28 MHz

ADCCLK pulse duration, clock high, t

w(MCLKH)

17.8 ns

ADCCLK pulse duration, clock low, t

w(MCLKL)

17.8 ns

Input SCLK frequency 40 MHz

SCLK pulse duration, clock high, t

w(SCLKH)

12.5 ns

SCLK pulse duration, clock low, t

w(SCLKL)

12.5 ns

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