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SDO

SDI

SCLK

EOC/(INT

)

REFP

REFM

PWDN

GND

CSTART

PW PACKAGE

(TOP VIEW)

TLV2548-EP

www.ti.com

SLAS668 –OCTOBER 2009

3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL

ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN

Check for Samples: TLV2548-EP

FEATURES

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

• Maximum Throughput 200-KSPS

• Controlled Baseline

• Built-In Reference, Conversion Clock and

• One Assembly/Test Site

8x FIFO

• One Fabrication Site

• Differential/Integral Nonlinearity Error: ±1.2

• Available in Military (–55°C/125°C)

LSB

Temperature Range

(1)

• Signal-to-Noise and Distortion Ratio: 70 dB,

• Extended Product Life Cycle

= 12 kHz

• Extended Product-Change Notification

• Spurious Free Dynamic Range: 75 dB,

• Product Traceability

= 12 kHz

• SPI (CPOL = 0, CPHA = 0)/DSP-Compatible

Serial Interfaces With SCLK up to 20 MHz

• Single Wide Range Supply 3.0 Vdc to 5.5 Vdc

• Analog Input Range 0 V to Supply Voltage

With 500-kHz BW

• Hardware Controlled and Programmable

Sampling Period

• Low Operating Current (1.0 mA at 3.3 V,

2.0 mA at 5.5 V With External Ref, 1.7-mA at

3.3V, 2.4-mA at 5.5-V With Internal Ref)

• Power Down: Software/Hardware

Power-Down Mode (1 μA Max, Ext Ref),

Autopower-Down Mode (1 μA, Ext Ref)

• Programmable Auto-Channel Sweep (1) Custom temperature ranges available

DESCRIPTION

The TLV2548 is a high performance, 12-bit low-power, 3.86-μs, CMOS analog-to-digital converter (ADC) which

operates from a single 3.0-V to 5.5-V power supply. This device has three digital inputs and a 3-state output [chip

select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a

direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced

with a TI DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame.

In addition to a high-speed A/D converter and versatile control capability, this device has an on-chip analog

multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold

function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special

pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be

programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular among

high-performance signal processors. The TLV2548 is designed to operate with very low power consumption. The

power-saving feature is further enhanced with software/hardware/autopower-down modes and programmable

conversion speeds. The conversion clock (OSC) and reference are built-in. The converter can use the external

SCLK as the source of the conversion clock to achieve higher (up to 2.8 μs when a 20-MHz SCLK is used)

conversion speed. Two different internal reference voltages are available. An optional external reference can also

be used to achieve maximum flexibility.

The TLV2548 is characterized for operation from –55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLV2548-EP

www.ti.com

SLAS668 –OCTOBER 2009

Table 2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O DESCRIPTION

NAME NO.

This terminal controls the start of sampling of the analog input from a selected multiplex

channel. Sampling time starts with the falling edge of CSTART and ends with the rising edge

of CSTART as long as CS is held high. In mode 01, select cycle, CSTART can be issued as

CSTART 14 I

soon as CHANNEL is selected which means the fifth SCLK during the select cycle, but the

effective sampling time is not started until CS goes to high. The rising edge of CSTART

(when CS = 1) also starts the conversion. Tie this terminal to V

if not used.

End of conversion or interrupt to host processor. [PROGRAMMED AS EOC]: This output

goes from a high-to-low logic level at the end of the sampling period and remains low until

the conversion is complete and data are ready for transfer. EOC is used in conversion mode

00 only.

EOC/(INT) 4 O

xxx

[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to

the host processor. The falling edge of INT indicates data are ready for output. The following

CS↓ or FS clears INT.

DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If

FS remains low after the falling edge of CS, SDI is not enabled until an active FS is

presented. A high-to-low transition on the FS input resets the internal 4-bit counter and

FS 17 I enables SDI within a maximum setup time. SDI is disabled within a setup time after the 4-bit

counter counts to 16 (clock edges) or a low-to-high transition of CS whichever happens first.

xxx

Tie this terminal to V

if not used. See the Data Code Information section, item 1.

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements

GND 15 I

are with respect to GND.

Both analog and reference circuits are powered down when this pin is at logic zero. The

PWDN 16 I device can be restarted by active CS, FS or CSTART after this pin is pulled back to logic

one.

Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is

used to clock the input SDI to the input register. When programmed, it may also be used as

SCLK 3 I the source of the conversion clock.

NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when

idling for SPI compatible interface.

Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,

D(15−12) are decoded as one of the 16 commands. The configure write commands require

an additional 12 bits of data.

xxx

When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS

and is latched in on the rising edges of SCLK (after CS↓).

SDI 2 I

xxx

When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected

after the falling edge of FS and is latched in on the falling edges of SCLK.

xxx

SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock edges) or a

low-to-high transition of CS whichever happens first.

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance

state when CS is high and after the CS falling edge and until the MSB is presented. The

output format is MSB first.

xxx

When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO

pin after the CS falling edge, and successive data are available at the rising edge of SCLK

and changed on the falling edge.

xxx

SDO 1 O When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the

falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge

of SCLK and changed on the rising edge. (This is typically used with an active FS from a

DSP.)

xxx

For conversion and FIFO read cycles, the first 12 bits are result from previous conversion

(data) followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should

be ignored. The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit.

See the Data Code Information section, item 2.

External reference input or internal reference decoupling. Tie this pin to analog ground if

REFM 18 I

internal reference is used.

Product Folder Link(s): TLV2548-EP

TLV2548-EP

www.ti.com

SLAS668 –OCTOBER 2009

OUTPUT DATA FORMAT CONVERSION

MSB LSB

D15−D4 D3−D0

Conversion result

Don’t care

OD[11:0]

The output data format is binary (unipolar straight binary).

Binary

Zero scale code = 000h, Vcode = VREFM.

Full scale code = FFFh, Vcode = VREFP − 1 LSB

Control and Timing

Power Up and Initialization Requirements

• Determine processor type by writing A000h to the TLV2548 (CS must be toggled).

• Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode;

i.e., active FS).

The first conversion after power up or resuming from power down is not valid.

Start of the Cycle

• When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.

• When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.

First 4-MSBs: The Command Register (CMR)

The TLV2548 has a 4-bit command set (see Table 3) plus a 12-bit configuration data field. Most of the

commands require only the first 4 MSBs, i.e., without the 12-bit data field.

The valid commands are listed in Table 3.

Table 3. TLV2548 Command Set

(1)

SDI D(15−12) BINARY COMMAND

0000b 0h Select analog input channel 0

0001b 1h Select analog input channel 1

0010b 2h Select analog input channel 2

0011b 3h Select analog input channel 3

0100b 4h Select analog input channel 4

0101b 5h Select analog input channel 5

0110b 6h Select analog input channel 6

0111b 7h Select analog input channel 7

1000b 8h SW power down (analog + reference)

1001b 9h Read CFR register data shown as SDO D(11-0)

Write CFR followed by 12–bit data, e.g., 0A100h means external reference,

1010b Ah plus data

short sampling, SCLK/4, single shot, INT

1011b Bh Select test, voltage = (REFP+REFM)/2

1100b Ch Select test, voltage = REFM

1101b Dh Select test, voltage = REFP

1110b Eh FIFO read, FIFO contents shown as SDO D(15-4), D(3-0) = 0000

1111b Fh plus data Reserved

(1) The status of the CFR can be read with a read CFR command when the device is programmed for one–shot conversion mode

(CFR D[6,5] = 00).

Product Folder Link(s): TLV2548-EP

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