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TI-TLV710.pdf
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TI-TLV710.pdf
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OUT1
OUT2
GND
6
5
4
EN1
IN
EN2
1
2
3
TLV710
TLV711
1.5mmx1.5mmSON-6
(TOPVIEW)
IN
EN1
EN2
GND
OUT1
OUT2
ON
OFF
ON
OFF
V
IN
C
IN
C
1 F
Ceramic
m
OUT1
C
OUT2
1 F
Ceramic
m
V
OUT1
V
OUT2
TLV710 Series
TLV711 Series
www.ti.com.cn
ZHCS452A –JULY 2010– REVISED AUGUST 2010
适合便携式设备的双通道、
200mA、低 I
Q
、 低 压 降 稳 压 器
1
特性 说明
2
• 超低的压降:
TLV710 和 TLV711 系列双通道、低压降 (LDO) 线性
稳压器是具有卓越的线路输入电压及负载瞬态响应性能
– 150mV(在 I
OUT
=200mA 和 V
OUT
= 2.8V 时)
的低静态电流器件。 这些 LDO 专门针对功耗敏感型应
– 75mV(在 I
OUT
=100mA 和 V
OUT
= 2.8V时)
用而设计。 这些器件在整个温度范围内提供了2% 的
– 40mV(在 I
OUT
=50mA 和 V
OUT
= 2.8V时)
典型准确度。
• 在整个温度范围内可提供 2% 的准确度
• 低I
Q
:每个稳压器为 35μA
TLV711系列提供了一种有源下拉电路,以对输出进行
• 可提供多种固定输出电压组合:1.2V至4.8V
快速放电。
• 高PSRR:70dB(在 1kHz 频率下)
此外,TLV711-D 器件系列还在 EN 引脚上布设了下拉
• 可在采用 0.1μF 的有效电容时保持稳定
(1)
电阻器。 这种设计有助于在信号驱动 EN 引脚处于一
• 过流和热保护
种微弱、不确定状态(例如:在启动期间有可能为三态
• 用于每个输出的专用 V
REF
最大限度地降低了串扰
的处理器 GPIO)时停用器件。 该下拉电阻器可将至
• 采用1.5mm x 1.5mm SON-6 封装
EN 引脚的电压拉低至 0V,从而停用器件。
(1)
请参见 应用信息部分中的 输入和输出电容器要求
TLV710 和 TLV711系列采用 1.5mm x 1.5mm SON-6
应用
封装,而且非常适合于手持式应用。
• 无线头戴式耳机、智能手机、PDA
• MP3 播放器及其他手持式产品
图 1. 典型应用电路
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not English Data Sheet: SBVS142A
necessarily include testing of all parameters.
TLV710 Series
TLV711 Series
ZHCS452A –JULY 2010– REVISED AUGUST 2010
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TLV710xxyyqwwwz XX is nominal output voltage of channel 1 (for example 18 = 1.8V).
TLV711xxyyqwwwz YY is nominal output voltage of channel 2 (for example 28 = 2.8V).
Q is optional. Use "U" for devices with EN pin pull-up resistor, and "D" for devices with EN pin pull-down resistor.
WWW is package designator.
Z is package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.2V to 4.8V in 50mV increments are available through the use of innovative factory OTP programming; minimum
order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
(1)
At T
J
= –40°C to +125°C (unless otherwise noted).
VALUE
MIN MAX UNIT
IN –0.3 +6.0 V
Voltage
(2)
EN –0.3 V
IN
+ 0.3 V
OUT –0.3 +6.0 V
Current OUT Internally limited A
Output short-circuit duration Indefinite s
Operating junction, T
J
–55 +150 °C
Temperature
Storage, T
stg
–55 +150 °C
Human body model (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic Discharge Rating
Charged device model (CDM) QSS 009-147
500 V
(JESD22-C101B.01)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages with respect to ground.
THERMAL INFORMATION
(1)
TLV710, TLV711
THERMAL METRIC
(2)
DSE UNITS
6 PINS
ψ
JT
Junction-to-top characterization parameter 6 °C/W
(1) See the Power Dissipation section for more details.
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Copyright © 2010, Texas Instruments Incorporated
TLV710 Series
TLV711 Series
www.ti.com.cn
ZHCS452A –JULY 2010– REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
At T
J
= +25°C, V
IN
= V
OUT(TYP)
+ 0.5V or 2.0V (whichever is greater), I
OUT
= 10mA, V
EN1
= V
EN2
= 0.9V, and C
OUT1
= C
OUT2
=
1μF, unless otherwise noted.
TLV710, TLV711
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range 2.0 5.5 V
V
O
Output voltage range 1.2 4.8 V
V
OUT
DC output accuracy –40°C ≤ T
J
≤ +125°C –2 +2 %
ΔV
O
/ΔV
IN
Line regulation V
OUT(NOM)
+ 0.5V ≤ V
IN
≤ 5.5V 1 5 mV
ΔV
O
/ΔI
OUT
Load regulation 0mA ≤ I
OUT
≤ 200mA 5 15 mV
V
IN
= 0.98V × V
OUT(NOM)
, I
OUT
= 200mA,
200 285 mV
2V ≤ V
OUT
< 2.4V
V
IN
= 0.98V × V
OUT(NOM)
, I
OUT
= 200mA,
175 250 mV
2.4V ≤ V
OUT
< 2.8V
V
DO
Dropout voltage
V
IN
= 0.98V × V
OUT(NOM)
, I
OUT
= 200mA,
150 215 mV
2.8V ≤ V
OUT
< 3.3V
V
IN
= 0.98V × V
OUT(NOM)
, I
OUT
= 200mA,
140 200 mV
3.3V ≤ V
OUT
≤ 4.8V
I
CL
Output current limit V
OUT
= 0.9V × V
OUT(NOM)
220 350 550 mA
V
EN1
= high, V
EN2
= low, I
OUT1
= 0mA 35 μA
I
Q
Quiescent current V
EN1
= low, V
EN2
= high, I
OUT2
= 0mA 35 μA
V
EN1
= high, V
EN2
= high, I
OUT
= 0mA 70 110 µA
I
GND
Ground pin current I
OUT1
= I
OUT2
= 200mA 360 µA
I
SHUTDOWN
Shutdown current V
EN1,2
≤ 0.4V, 2.0V ≤ V
IN
≤ 4.5V 2.5 4 μA
f = 10Hz 80 dB
f = 100Hz 75 dB
PSRR Power-supply rejection ratio V
OUT
= 1.8V f = 1kHz 70 dB
f = 10kHz 70 dB
f = 100kHz 50 dB
V
N
Output noise voltage BW = 100Hz to 100kHz, V
OUT
= 1.8V 48 μV
RMS
t
STR
Startup time
(1)
C
OUT
= 1.0μF, I
OUT
= 200mA 100 μs
V
HI
Enable high (enabled) 0.9 V
IN
V
V
LO
Enable low (shutdown) 0 0.4 V
TLV710, TLV711 0.04 μA
I
EN
Enable pin current, enabled
TLV710-D, TLV711-D 6 μA
UVLO Undervoltage lockout V
IN
rising 1.9 V
T
J
Operating junction temperature –40 +125 °C
Shutdown, temperature increasing +165 °C
T
SD
Thermal shutdown temperature
Reset, temperature decreasing +145 °C
(1) Startup time = time from EN assertion to 0.98 x V
OUT(NOM)
.
Copyright © 2010, Texas Instruments Incorporated 3
T ermalh
Shutdown
UVLO
TLV710-D
and
TLV711-D
only
TLV711andTLV711-Donly
TLV710-D
and
TLV711-D
only
OUT1
OUT2
EN2
EN1
IN
120W
120W
150kW
Thermal
Shutdown
UVLO
GND
Current
Limit
Current
Limit
Bandgap
Bandgap
Enable
and
Power
Control
Log ci
TLV711andTLV711-Donly
TLV710 Series
TLV711 Series
ZHCS452A –JULY 2010– REVISED AUGUST 2010
www.ti.com.cn
FUNCTIONAL BLOCK DIAGRAM
4 Copyright © 2010, Texas Instruments Incorporated
OUT1
OUT2
GND
6
5
4
EN1
IN
EN2
1
2
3
TLV710 Series
TLV711 Series
www.ti.com.cn
ZHCS452A –JULY 2010– REVISED AUGUST 2010
PIN CONFIGURATION
DSE PACKAGE
1.5mm x 1.5mm SON-6
(TOP VIEW)
PIN DESCRIPTIONS
NAME PIN NO. DESCRIPTION
Enable pin for regulator 1. Driving EN1 over 0.9V turns on regulator 1. Driving EN below 0.4V puts regulator
EN1 1
1 into shutdown mode.
Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output
IN 2
Capacitor Requirements in the Application Information section for more details.
Enable pin for regulator 2. Driving EN2 over 0.9V turns on regulator 2. Driving EN2 below 0.4V puts
EN2 3
regulator2 into shutdown mode.
GND 4 Ground pin.
Regulated output voltage pin. A small 1μF ceramic capacitor is needed from this pin to ground to assure
OUT2 5 stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
Regulated output voltage pin. A small 1μF ceramic capacitor is needed from this pin to ground to assure
OUT1 6 stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
Copyright © 2010, Texas Instruments Incorporated 5
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