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TLV841 Small Size Nano-Power Voltage Supervisor in WCSP Package

1 Features

Designed for high performance:

• Nano quiescent current: 125 nA (typical)

• High threshold accuracy: ±0.5% (typical)

• Built-in precision hysteresis (V

HYS

): 5% (typical)

Designed for a wide range of applications:

• Operating voltage range: 0.7 V to 5.5 V

• Adjustable threshold voltage: 0.505 V (typical)

• Fixed (V

IT-

) voltage: 0.8 V to 4.9 V in 0.1 V steps

• Separate SENSE pin (TLV841S)

• Active-low manual reset (MR) (TLV841M)

• Push-button monitoring for TLV841 (S/M variants)

• Reset time delay (t

): Capacitor-based

programmable (TLV841C)

– Min time delay: 40 µs (typical) without capacitor

• Reset time delay (t

): Fixed time delay options

(TLV841M and TLV841S)

– 40 μs, 2 ms, 10 ms, 30 ms, 50 ms, 80 ms,

100 ms, 150 ms, 200 ms

• Temperature range: –40°C to +125°C

Multiple output topologies, package type:

• TLV841xxDL: open-drain, active-low (RESET)

• TLV841xxPL: push-pull, active-low (RESET)

• TLV841xxDH: open-drain, active-high (RESET)

• TLV841xxPH: push-pull, active-high (RESET)

• Package: 0.73-mm x 0.73-mm DSBGA

2 Applications

• Personal electronics including wearables and

hearing devices

• Home theater and entertainment

• Electronic point of sale

• Grid infrastructure

• Data center and enterprise computing

3 Description

TLV841 is a nano power, precision voltage supervisor

with ±0.5% threshold accuracy in an ultra small

DSBGA package. The TLV841 offers three pinout

variants (S, M, C) to provide many unique options

in the smallest total solution size in its class. Built-

in hysteresis along with fixed or programmable

(TLV841C) reset delay prevent false reset signals

when monitoring a voltage rail or push button signals.

On active-low outputs of TLV841S, increasing the

voltage threshold hysteresis can be achieved by

adding an external resistor between the SENSE and

RESET pins. TLV841 with its precision performance,

low power consumption, and best in-class features

in the smallest compact form factor, offers an ideal

solution for wide range battery powered applications

such as personal and consumer products.

The separate VDD and SENSE (TLV841S) pins allow

for the redundancy sought by high-reliability systems.

SENSE is decoupled from VDD and can monitor rail

voltages other than VDD or can be used as a push-

button input. Optional use of external resistors are

supported by the high impedance input of the SENSE

pin. TLV841S offers fixed reset delay timing options

with no need of an external capacitor. TLV841C

allows programmable reset time delay including a

minimum delay when the CT pin is left floating.

TLV841M offers a separate manual reset (MR) pin to

force a reset condition with an external signal or be

used as a push button input. TLV841M can be setup

for VDD and MR pin monitoring to create a simple

two-channel supervisor solution. TLV841 operates

over a temperature range of -40°C to +125°C (T

Device Information

PART NUMBER PACKAGE

(1)

BODY SIZE (NOM)

TLV841 DSBGA (4) 0.73 mm × 0.73 mm

(1) For package details, see the mechanical drawing addendum

at the end of the data sheet.

TLV841SADL01

VDD

GND

Microcontroller

VDD

0.7 V to 5.5 V

LDO

SENSE

OUT

only for TLV841xxDx

RESET

Typical Application Circuit

VDD (V)

IDD ( A)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

0.2

0.4

0.6

0.8

-40

C 25

C 125

Typical Supply Current

TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison......................................................... 3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................7

7.6 Timing Requirements ................................................. 9

7.7 Timing Diagrams ...................................................... 10

7.8 Typical Characteristics.............................................. 12

8 Detailed Description......................................................13

8.1 Overview................................................................... 13

8.2 Functional Block Diagram......................................... 13

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................19

9 Application and Implementation.................................. 20

9.1 Application Information............................................. 20

9.2 Typical Application.................................................... 20

10 Power Supply Recommendations..............................23

11 Layout...........................................................................24

11.1 Layout Guidelines................................................... 24

11.2 Layout Example...................................................... 24

12 Device and Documentation Support..........................25

12.1 Device Nomenclature..............................................25

12.2 Documentation Support.......................................... 27

12.3 Receiving Notification of Documentation Updates..27

12.4 Support Resources................................................. 27

12.5 Trademarks.............................................................27

12.6 Electrostatic Discharge Caution..............................27

12.7 Glossary..................................................................27

13 Mechanical, Packaging, and Orderable

Information.................................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2021) to Revision C (June 2021) Page

• RTM of device.....................................................................................................................................................1

TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

www.ti.com

2 Submit Document Feedback

Product Folder Links: TLV841

6 Pin Configuration and Functions

RESET / RESET

VDD

GND

SENSE

A1 A2

B1 B2

Figure 6-1. YBH 4-Pin DSBGA Package

(TLV841S)

Top View

VDD

GND

A1 A2

B1 B2

RESET / RESET

Figure 6-2. YBH 4-Pin DSBGA Package

(TLV841C)

Top View

VDD

GND

A1 A2

B1 B2

RESET / RESET

Figure 6-3. YBH 4-Pin DSBGA Package

(TLV841M)

Top View

Table 6-1. Pin Functions

I/O DESCRIPTION

PIN NO. TLV841S TLV841C TLV841M

A1 RESET RESET RESET O

Active-Low Output Reset Signal for TLV841xxxL: This pin is driven logic low

when VDD and SENSE voltage falls below the negative voltage threshold (V

IT-

) or

when the MR voltage falls below the logic low threshold. RESET remains logic low

(asserted) until MR is above the logic high threshold or for the duration of the delay

time period (t

) after VDD or SENSE voltage rises above V

IT-

+ V

HYS

A1 RESET RESET RESET O

Active-High Output Reset Signal for TLV841xxxH: This pin is driven logic high

when VDD or SENSE voltage falls below the negative voltage threshold (V

IT-

) or

when the MR voltage falls below the logic low threshold. RESET remains logic high

(asserted) until MR is above the logic high threshold or for the duration of the delay

time period (t

) after VDD or SENSE voltage rises above V

IT-

+ V

HYS

A2 VDD VDD VDD I

Input Supply Voltage: The VDD pin connects to the power supply to power the

device. TLV841C and TLV841M monitor VDD voltage. TLV841S monitors SENSE

only. Good analog design practice recommends placing a minimum 0.1 µF ceramic

capacitor as near as possible to the VDD pin.

B1 SENSE _ _ I

SENSE pin: This pin is connected to the voltage to be monitored. When the voltage

on SENSE falls below the negative threshold voltage V

IT-

, reset asserts. When the

voltage on SENSE rises above the positive threshold voltage (V

IT-

+ V

HYS

), reset

deasserts. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close

to this pin may be needed for optimum performance.

B1 _ CT _ I

Capacitor Time Delay Pin: The CT pin offers a user-programmable reset deassert

delay time. Connect an external capacitor on this pin to adjust time delay. When not

in use leave pin floating for the smallest fixed time delay.

B1 _ _ MR I

Manual Reset: Pull this pin to a logic low to assert a reset signal in the RESET

output pin (RESET signal for DL and PL option). After MR pin is left floating or pulls

to logic high, the RESET output deasserts to the nominal state after the reset delay

time (t

)expires. If unused, the pin can be left floating or connected to VDD.

B2 GND GND GND _ Ground

TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

www.ti.com

4 Submit Document Feedback

Product Folder Links: TLV841

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted

(1)

MIN MAX UNIT

Voltage VDD, SENSE (TLV841S) –0.3 6 V

Voltage

CT (TLV841C), MR (TLV841M), RESET

(TLV841xxPx), RESET (TLV841xxPx)

–0.3 V

+0.3

(3)

RESET (TLV841xxDx), RESET (TLV841xxDx) –0.3 6

Current RESET, RESET ±20 mA

Temperature

(2)

Operating ambient temperature, T

–40 125

°C

Temperature Storage, T

stg

–65 150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) As a result of the low dissipated power in this device, it is assumed that T

= T

(3) The absolute maximum rating is (VDD + 0.3) V or 6 V, whichever is smaller

7.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001

(1)

± 2000

Charged device model (CDM), per JEDEC specification

JESD22-C101

(2)

± 750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Voltage

VDD (TLV841C, TLV841M) 0.7 5.5

VDD (TLV841S) 0.85 5.5

VDD (TLV841xxPH) 1 5.5

SENSE 0 5.5

(1)

, CT 0 V

RESET(TLV841xxPL), RESET (TLV841xxPH) 0 V

RESET(TLV841xxDL), RESET (TLV841xxDH) 0 5.5

Current RESET, RESET –5 5 mA

Operating free air temperature –40 125 °C

CT pin capacitor range 0 10 µF

(1) If the logic signal driving MR is less than V

, then additional current flows into VDD and out of MR. MR pin voltage should not be

higher than V

DD.

www.ti.com

TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

Submit Document Feedback

Product Folder Links: TLV841

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