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FPD-Link转换器
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DS99R124Q
www.ti.com
SNLS318D –JANUARY 2010–REVISED APRIL 2013
DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
Check for Samples: DS99R124Q
1
FEATURES
DESCRIPTION
The DS99R124Q converts FPD-Link II to FPD-Link. It
2
• 5 – 43 MHz Support (140 Mbps to 1.2 Gbps
translates a high-speed serialized interface with an
Serial Link)
embedded clock over a single pair (FPD-Link II) to
• 4-Channel (3 data + 1 Clock) FPD-Link LVDS
three LVDS data/control streams and one LVDS clock
Outputs
pair (FPD-Link). This serial bus scheme greatly eases
system design by eliminating skew problems between
• 3 Low-Speed Over-Sampled LVCMOS Outputs
clock and data, reduces the number of connector
• AC Coupled STP Interconnect up to 10 Meters
pins, reduces the interconnect size, weight, and cost,
in Length
and overall eases PCB layout. In addition, internal
• Integrated Input Termination
DC balanced decoding is used to support AC-coupled
interconnects.
• @ Speed Link BIST Mode and Reporting Pin
• Optional I2C Compatible Serial Control Bus
The DS99R124Q converter recovers the data (RGB)
and control signals and extracts the clock from a
• RGB666 + VS, HS, DE Converted from 1 Pair
serial stream (FPD-Link II). It is able to lock to the
• Power Down Mode Minimizes Power
incoming data stream without the use of a training
Dissipation
sequence or special SYNC patterns and does not
• FAST Random Data Lock; no Reference Clock
require a reference clock. A link status (LOCK) output
Required
signal is provided.
• Adjustable Input Receive Equalization
Adjustable input equalization of the serial input
stream provides compensation for transmission
• LOCK (Real Time Link Status) Reporting Pin
medium losses of the cable and reduces the medium-
• Low EMI FPD-Link Output
induced deterministic jitter. EMI is minimized by the
• SSCG Option for Lower EMI
use of low voltage differential signaling, output state
• 1.8V or 3.3V Compatible I/O Interface
select feature, and additional output spread spectrum
generation.
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
With fewer wires to the physical interface of the
display, FPD-Link output with LVDS technology is
• >8 kV HBM and ISO 10605 ESD Rating
ideal for high speed, low power and low EMI data
transfer.
APPLICATIONS
The DS99R124Q is offered in a 48-pin WQFN
• Automotive Display for Navigation
package and is specified over the automotive AEC-
• Automotive Display for Entertainment
Q100 Grade 2 temperature range of -40˚C to +105˚C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DS99R124Q
TOP VIEW
DAP = GND
GND
VDDP
GND
GND
RIN-
RIN+
VDDA
RES[1]
VDDTX
GND
ID[x]
TxCLKOUT+
TxOUT2-
TxOUT1+
TxOUT0+
TxOUT0-
GND
CMF
VDDA
VDDP RES[0]
TxCLKOUT-
TxOUT2+
TxOUT1-
PDB
SSC[0]
OS[2]
OS[0]
SSC[1]
OSS_SEL
OEN
VODSEL
GND
VDDL
BISTM
BISTEN
PASS/EQ
LOCK
GND
LFMODE
SSC[2]
VDDP
OS[1]
VDDIO
GND
SDA
SCL
VDDL
PWDNB
100 ohm STP Cable
PASS
PDB
LFMODE
BISTEN
LOCK
RGB Style Display Interface
RGB Display
QVGA to WVGA
18-bit Color Depth
DS99R421Q
Converter
DS99R124Q
Converter
High-Speed Serial Link
1 Pair/AC Coupled
SSC[2:0]
OEN
VODSEL
BISTM
OSSEL
3.3V
FPD-Link II
FPD-Link
CMF
FPD-Link
RxIN1+/-
RxCLKIN+/-
RxIN2+/-
RxIN0+/-
TxOUT1+/-
TxCLKOUT+/-
TxOUT2+/-
TxOUT0+/-
3.3V
VDDIO
(1.8V or 3.3V)
1.8V
SDA
ID[x]
SCL
Optional
HOST
Graphics
Processor
DOUT+
DOUT-
RIN+
RIN-
OS[2:0]
VODSEL
DEN
BISTEN
PRE
OS[2:0]
DS99R124Q
SNLS318D –JANUARY 2010–REVISED APRIL 2013
www.ti.com
Applications Diagram
Figure 1.
DS99R124Q Pin Diagram
Figure 2. FPD-Link II to FPD-Link Convertor - DS99R124Q
48 Pin WQFN Package
See Package Number RHS0048A
2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS99R124Q
DS99R124Q
www.ti.com
SNLS318D –JANUARY 2010–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name Pin # I/O, Type Description
FPD-Link II Input Interface
RIN+ 40 I, LVDS True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
RIN- 41 I, LVDS Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
CMF 42 I, Analog Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[2:0]+ 19, 21, 23 O, LVDS True LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxOUT[2:0]- 20, 22, 24 O, LVDS Inverting LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxCLKOUT+ 17 O, LVDS True LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxCLKOUT- 18 O, LVDS Inverting LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
LVCMOS Outputs
OS[2:0] 10, 11, 12 O, LVMOS Over-Sampled Low Frequency Outputs
These bits map to the DS99R421's OS[2:0] over-sampled low-frequency inputs. Signals must
be slower the TxCLK/5. On the DS90UR241 these map to the DIN[23:21] inputs. OS0 =
DIN21, OS1 = DIN22, OS2 = DIN23.
LOCK 27 O, LVMOS LOCK Status Output
LOCK = 1, PLL is locked, outputs are active.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL.
Maybe used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB 1 I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the output are controlled by the settings. Control registers
are RESET.
VODSEL 33 I, LVCMOS Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
See Table 2
OEN 34 I, LVCMOS Output Enable Input
w/ pull-down OEN = 1, FPD-Link outputs are enabled (active).
OEN = 0, FPD-Link outputs are TRI-STATE.
OSS_SEL 35 I, LVCMOS Output Sleep State Select Input
w/ pull-down See Table 1
LFMODE 36 I, LVCMOS Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-43 MHz)
SSC[2:0] 7, 2, 3 I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select
w/ pull-down See Table 3 and Table 4
RES[1:0] 37, 15 I, LVCMOS Reserved
w/ pull-down Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon power-
up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ 28 [PASS] STRAP EQ Gain Control of FPD-Link II Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
Optional BIST Mode
BISTEN 29 I, LVCMOS BIST Enable Input – Optional
w/ pull-down BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS99R124Q
RIN-
DS99R124Q ± CONVERTER
RIN+
PLL
Timing and
Control
3
LOCK
OS[2:0]
SSCG
Serializer
Serial to Parallel
DC Balance Decoder
PASS
SSC[2:0]
OEN
VODSEL
TxOUT[2]
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
TxOUT[1]
TxOUT[0]
TxCLKOUT
BISTM
OSS_SEL
LFMODE
DS99R124Q
SNLS318D –JANUARY 2010–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS (continued)
Pin Name Pin # I/O, Type Description
BISTM 30 I, LVCMOS BIST Mode Input – Optional
w/ pull-down BISTM = 1, selects Payload Error Mode
BISTM = 0, selects Pass / Fail Result-Only Mode
PASS 28 O, LVCMOS PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL 5 I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
DDIO
.
SDA 4 I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
ID[x] 16 I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 5.
Power and Ground
VDDL 6, 31 Power Logic Power, 1.8 V ±5%
VDDA 38, 43 Power Analog Power, 1.8 V ±5%
VDDP 8, 46, 47 Power SSC Generator Power, 1.8 V ±5%
VDDTX 13 Power FPD-Link Power, 3.3 V ±10%
VDDIO 25 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND 9, 14, 26, Ground Ground
32, 39, 44,
45, 48
DAP DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
Block Diagram
Figure 3. FPD-Link II to FPD-Link Convertor
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS99R124Q
DS99R124Q
www.ti.com
SNLS318D –JANUARY 2010–REVISED APRIL 2013
Absolute Maximum Ratings
(1)(2)
Supply Voltage – V
DDn
(1.8V) −0.3V to +2.5V
Supply Voltage – V
DDTX
(3.3V) −0.3V to +4.0V
Supply Voltage – V
DDIO
−0.3V to +4.0V
LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V)
Receiver Input Voltage −0.3V to (VDD + 0.3V)
LVDS Output Voltage −0.3V to (VDDTX + 0.3V)
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4s) +260°C
48L RHS Package
Maximum Power Dissipation Capacity at Derate above 25°C 1/ θ
JA
°C/W
25°C
θ
JA
27.7 °C/W
θ
JC
3.0 °C/W
ESD Rating (IEC, powered-up only), R
D
= Air Discharge (R
IN+
, R
IN−
) ≥±30 kV
330Ω, C
S
= 150pF
Contact Discharge (R
IN+
, R
IN−
) ≥±6 kV
ESD Rating (ISO10605), R
D
= 330Ω, C
S
= Air Discharge (R
IN+
, R
IN−
) ≥±15 kV
150 & 330pF
Contact Discharge (R
IN+
, R
IN−
) ≥±8 kV
ESD Rating (ISO10605), R
D
= 2kΩ, C
S
= 150 Air Discharge (R
IN+
, R
IN−
) ≥±15 kV
& 330pF
Contact Discharge (R
IN+
, R
IN−
) ≥±8 kV
ESD Rating (HBM) ≥±8 kV
ESD Rating (CDM) ≥±1.25 kV
ESD Rating (MM) ≥±250 V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min Nom Max Units
Supply Voltage (V
DDn
) 1.71 1.8 1.89 V
LVCMOS Supply Voltage (V
DDIO
) 1.71 1.8 1.89 V
LVCMOS Supply Voltage (V
DDIO
) 3.0 3.3 3.6 V
Operating Free Air Temperature (T
A
) −40 +25 +105 °C
TxCLK Clock Frequency 5 43 MHz
Supply Noise
(1)
100 mV
P-P
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V
DDn
(1.8V) supply with
amplitude = 100 mVp-p measured at the device V
DDn
pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS99R124Q
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