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TI-LMP91051.pdf
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LMP91051
www.ti.com
SNAS581B –MARCH 2012–REVISED MAY 2013
LMP91051 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications
Check for Samples: LMP91051
1
FEATURES
DESCRIPTION
2
• Dual Channel Input
The LMP91051 is a dual channel programmable
• Programmable Gain Amplifier
integrated Sensor Analog Front End (AFE) optimized
• “Dark Signal” Offset Cancellation
for thermopile sensors, as typically used in NDIR
applications. It provides a complete signal path
• Supports External Filtering
solution between a sensor and microcontroller that
• Common Mode Generator and 8 Bit DAC
generates an output voltage proportional to the
• Package 14 Pin TSSOP
thermopile voltage. The LMP91051’s programmability
enables it to support multiple thermopile sensors with
APPLICATIONS
a single design as opposed to the multiple discrete
solutions.
• NDIR Sensing
The LMP91051 features a programmable gain
• Demand Control Ventilation
amplifier (PGA), “dark phase” offset cancellation, and
• Building Monitoring
an adjustable common mode generator (1.15V or
• CO2 Cabin Control — Automotive
2.59V) which increases output dynamic range. The
PGA offers a low gain range of 167V/V to 1335V/V
• Alcohol Detection — Automotive
plus a high gain range of 1002V/V to 7986V/V which
• Industrial Safety and Security
enables the user to utilize thermopiles with different
• GHG & Freons Detection Platforms
sensitivities. The PGA is highlighted by low gain drift
(20 ppm/°C), output offset drift (230 mV/°C at
KEY SPECIFICATIONS
G = 1002 V/V), phase delay drift (300 ns) and noise
specifications (0.1 µVRMS 0.1 to 10Hz) . The offset
• Programmable Gain … 167V/V to 7986V/V
cancellation circuitry compensates for the “dark
• Low Noise (0.1 to 10 Hz) … 0.1µVRMS
signal” by adding an equal and opposite offset to the
• Gain Drift … 20 ppm/°C (typ)
input of the second stage, thus removing the original
offset from the output signal. This offset cancellation
• Phase Delay Drift … 300 ns (typ)
circuitry allows optimized usage of the ADC full scale
• Power supply voltage range … 2.7V to 5.5V
and relaxes ADC resolution requirements.
The LMP91051 allows extra signal filtering (high
pass, low pass or band pass) through dedicated pins
A0 and A1, in order to remove out of band noise. The
user can program through the on board SPI interface.
Available in a small form factor 14 pin TSSOP
package, the LMP91051 operates from –40 to
+105°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430
AVSS/DVSS
LMP91051
IN2
Active
Thermopile
OUT
A0 A1
VDD
CMOUT
IN1
VIO
A/D
VIO
DVCC
GND
CSB
SDIO
SCLK
GPIO
CLK
MOSI
VDD
AVCC
VDD
VIO
Reference
Thermopile
OUT
IN2
DAC
VREFCM GEN
G1=250,42
G2=4,8,16,32
VDD
LMP91051
CMOUT
+
-
PGA1
+
-
PGA2
A0 A1
CMOUT
IN1
SPI
GND
CSB
SCLK
SDIO
VIO
Optional
External
Filter
SPI
LMP91051
SNAS581B –MARCH 2012–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
Configurable AFE for NDIR
TYPICAL APPLICATION
Typical NDIR Sensing Application Circuit
2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMP91051
SVA-30180650
LMP91051
www.ti.com
SNAS581B –MARCH 2012–REVISED MAY 2013
CONNECTION DIAGRAM
PIN DESCRIPTIONS
PIN
I/O DESCRIPTION
NAME NO.
IN1 1 Analog Input Signal Input
IN2 2 Analog Input Signal Input
CMOUT 3 Analog Output Common Mode Voltage Output
A0 4 Analog Output First Stage Output
A1 5 Analog Input Second Stage Input
GND 6 Power Ground
NC 7 — No Connect
NC 8 — No Connect
OUT 9 Analog Output Signal Output, reference to the same potential as CMOUT
CSB 10 Digital Input Chip Select, active low
SCLK 11 Digital Input Interface Clock
SDIO 12 Digital Input / Output Serial Data Input / Output
VIO 13 Power Digital Input/Output Supply
VDD 14 Power Positive Supply
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMP91051
LMP91051
SNAS581B –MARCH 2012–REVISED MAY 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Human Body Model 1000
ESD Tolerance
(3)
V
Charged Device Model 250
VDD Supply Voltage –0.3 6.0 V
VIO Digital I/O supply –0.3 6.0 V
Voltage at Any Pin ––0.3 VDD + 0.3 V
Input Current at Any Pin 5 mA
Storage Temperature Range 65 150 °C
Junction Temperature
(4)
150 °C
For soldering specifications: see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of T
J(MAX)
, θ
JA
, and the ambient temperature, T
A
. The maximum allowable power
dissipation at any ambient temperature is P
DMAX
= (T
J(MAX)
- T
A
)/ θ
JA
All numbers apply for packages soldered directly onto a PC board.
OPERATING CHARACTERISTICS
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage 2.7 5.5 V
Junction Temperature Range
(2)
–40 105 °C
θ
JA
Package Thermal Resitance Package 14 pin TSSOP 140 °C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
(2) The maximum power dissipation is a function of T
J(MAX)
, θ
JA
, and the ambient temperature, T
A
. The maximum allowable power
dissipation at any ambient temperature is P
DMAX
= (T
J(MAX)
- T
A
)/ θ
JA
All numbers apply for packages soldered directly onto a PC board.
ELECTRICAL CHARACTERISTICS
(1)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, Bold values for T
A
= -40°C to +85°C unless
otherwise specified. All other limits apply to T
A
= T
J
= +25°C.
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
UNIT
Power Supply
VDD Supply Voltage 2.7 3.3 5.5 V
VIO Digital I/O supply 2.7 3.3 5.5 V
IDD Supply Current All analog block ON 3.1 3.6 4.2 mA
Power Down Supply Current All analog block OFF 45 75 121 µA
Digital Supply Current 8 µA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that T
J
= T
A
. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where T
J
> T
A
. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMP91051
LMP91051
www.ti.com
SNAS581B –MARCH 2012–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS
(1)
(continued)
The following specifications apply for VDD = 3.3V, VIO = 3.3V, VCM = 1.15V, Bold values for T
A
= -40°C to +85°C unless
otherwise specified. All other limits apply to T
A
= T
J
= +25°C.
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
UNIT
Offset Cancellation (Offset DAC)
Resolution 256 steps
LSB All gains 33.8 mV
DNL –1 +2 LSB
Error Output referred offset error, all gains ±100 mV
VDD –
Offset adjust Range Output referred, all gains 0.2 V
0.2
DAC settling time 480 µs
Programmable Gain Amplifier (PGA) 1st Stage, R
L
= 10 kΩ, C
L
= 15 pF
IBIAS Bias Current 5 200 pA
VINMAX
Referenced to CMOUT voltage, it refers
Max input signal High gain mode ±2 mV
_HGM
to the maximum voltage at the IN pin
before clipping; It includes dark voltage
VINMAX
Max input signal Low gain mode ±12 mV
of the thermopile and signal voltage.
_LGM
VOS Input Offset Voltage –165 µV
G _HGM Gain High gain mode 250 V/V
G_LGM Gain Low gain mode 42 V/V
GE Gain Error Both HGM and LGM 2.5 %
VDD –
VOUT Output Voltage Range 0.5 V
0.5
1mV input step signal, HGM, Vout
PhDly Phase Delay 6 µs
measured at Vdd/2
Phase Delay variation with 1mV input step signal, HGM, Vout
TCPhDly 416 ns
Temperature measured at Vdd/2,
SSBW Small Signal Bandwidth Vin = 1mVpp, Gain = 250 V/V 18 kHz
Cin Input Capacitance 100 pF
Programmable Gain Amplifier (PGA) 2nd Stage, R
S
= 1kΩ, C
L
= 1µF
VINMAX Max input signal GAIN = 4 V/V 1.65 V
VINMIN Min input signal 0.82 V
G Gain Programmable in 4 steps 4 32 V/V
GE Gain Error Any gain 2.5 %
VDD –
VOUT Output Voltage Range 0.2 V
0.2
100mV input sine 35kHz signal, Gain =
PhDly Phase Delay 8, VOUT measureed at 1.65V, RL = 10 1 µs
kΩ
Phase Delay variation with 250mV input step signal, Gain = 8, Vout
TCPhDly 84 ns
Temperature measured at Vdd/2
SSBW Small Signal Bandwidth Gain = 32 V/V 360 kHz
Cin Input Capacitance 5 pF
CLOAD,
OUT Pin Load Capacitance Series RC 1 µF
OUT
RLOAD,
OUT Pin Load Resistance Series RC 1 kΩ
OUT
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMP91051
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