TI-TPS2206A.pdf资源-CSDN文库

需积分: 9 86 浏览量 2022-11-14 23:05:33 上传评论 5 收藏 423KB PDF 举报

资源推荐

资源详情

资源评论







SLVS449A − DECEMBER 2002 − REVISED MAY 2003

   

     

FEATURES

D Fully Integrated V

and V

Switching for

Single-Slot or Dual-Slot PC Card Interface

D P

C 3-Lead Serial Interface Compatible With

CardBus Controller

D Meets PC Card Standard

D RESET for System Initialization of PC Cards

D 12-V Supplies Can Be Disabled Except During

12-V Flash Programming

D Short-Circuit and Thermal Protection

D 24-Pin HTSSOP (PWP), 30-Pin SSOP (DB),

and 32-Pin TSSOP (DAP) Packages

D Compatible With 3.3-V, 5-V, and 12-V PC

Cards

D Low r

DS(on)

(95-mΩ, 5-V V

Switch; 85-mΩ

3.3-V V

Switch)

D Single-Slot Switch: TPS2210A

Dual-Slot Switch: TPS2204A and TPS2206A

D Break-Before-Make Switching

APPLICATIONS

D Notebook and Desktop Computers

D Set-Top Boxes

D Personal Digital Assistants(PDAs)

D Digital Cameras

D Bar Code Scanners

DESCRIPTION

The TPS2204A and TPS2206A PC CardBus

power-interface switches provide an integrated

power-management solution for two PC Card sockets.

The TPS2210A is a single-slot option for this family of

devices. These devices allow the controlled distribution of

3.3 V, 5 V, and 12 V to each card slot. The current-limiting

and thermal-protection features eliminate the need for

fuses. Current-limit reporting helps the user isolate a

system fault. The switch r

DS(on)

and current-limit values

are set for the peak and average current requirements

stated in the PC Card specification, and are optimized for

cost.

The TPS2206A is pin and/or functionally compatible with

the TPS2206, TPS2216, TPS2216A, TPS2226,

TPS2226A, and TPS2228 with a few exceptions, as

shown in the Available Options table.

AVAILABLE OPTIONS OF THE TPS2206A PIN COMPATABLE SWITCHES

PART NUMBER

INDEPENDENT

PIN VARIATION

INPUT

PART NUMBER

INDEPENDENT

SWITCHING

RESET RESET SHDN MODE STBY

INPUT

VOLTAGES

TPS2206 No Yes Yes No No No 3.3 V, 5 V, 12 V

TPS2206A No Yes No Yes No No 3.3 V, 5 V, 12 V

TPS2216 Yes/No

(1)

Yes Yes No Yes Yes 3.3 V, 5 V, 12 V

TPS2216A Yes/No

(1)

Yes Yes No Yes Yes 3.3 V, 5 V, 12 V

TPS2226 Yes Yes No Yes No No 3.3 V, 5 V, 12 V

TPS2226A Yes Yes No Yes No No 3.3 V, 5 V, 12 V

TPS2228 Yes Yes No Yes No No 1.8 V, 3.3 V, 5 V

(1)

Selected by MODE pin.

   ! "#$ !  %#&'" ($) (#"!

"  !%$""! %$ *$ $!  $+! !#$! !(( ,-)

(#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!)

C is a trademark of Texas Instruments.

PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com







SLVS449A − DECEMBER 2002 − REVISED MAY 2003

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGED DEVICES

PLASTIC SMALL OUTLINE

(DB)

POWERPAD PLASTIC SMALL

OUTLINE (DAP−32)

POWERPAD PLASTIC SMALL

OUTLINE (PWP−24)

−40°C to 85°C TPS2206ADB TPS2206ADAP

TPS2204APWP

TPS2210APWP

(1)

The DB, PWP, and DAP packages are available taped and reeled. Add R suffix to device type (e.g., TPS2206ADBR) for taped and reeled.

PACKAGE DISSIPATION RATINGS

PACKAGE

(1)

≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE T

= 25°C

= 70°C

POWER RATING

= 85°C

POWER RATING

DB (30) 821.46 mW 10.95 mW/°C 328.58 mW 164.29 mW

DAP (32) 3191.4 mW 42.55 mW/°C 1276.5 mW 638.29 mW

PWP (24) 2491.6 mW 33.22 mW/°C 996.67 mW 498.33 mW

(1)

These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNITS

I(3.3V

) −0.3 V to 5.5 V

Input voltage range for card power

I(5V)

−0.3 V to 5.5 V

Input voltage range for card power

I(12V)

−0.3 V to 14 V

Logic input/output voltage −0.3 V to 6 V

Output voltage

O(xVCC)

−0.3 V to 6 V

Output voltage

O(xVPP)

−0.3 V to 14 V

Continuous total power dissipation See Dissipation Rating Table

Output current

O(xVCC)

Internally Limited

Output current

O(xVPP)

Internally Limited

Operating virtual junction temperature range, T

−40°C to 100 °C

Storage temperature range, T

STG

−55°C to 150 °C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) 260 °C

OC sink current 10 mA

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PowerPAD is a trademark of Texas Instruments.







SLVS449A − DECEMBER 2002 − REVISED MAY 2003

www.ti.com

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Input voltage, V

I(3.3V)

is required for all circuit operations. 5 V and

I(3.3V)(1)

3 3.6

Input voltage, V

I(3.3V)

is required for all circuit operations. 5 V and

12 V are only required for their respective functions.

I(5V)

3 5.5

12 V are only required for their respective functions.

I(12V)

7 13.5

Output current, I

O(xVCC)

at T

= 100°C 1 A

Output current, I

O(xVPP)

at T

= 100°C 100 mA

Clock frequency, f

(clock)

2.5 MHz

Data 200

Pulse duration, t

Latch 250

Pulse duration, t

Clock 100

Reset 100

Data-to-clock hold time, t

(see Figure 2) 100 ns

Data-to-clock setup time, t

(see Figure 2) 100 ns

Latch delay time, t

d(latch)

(see Figure 2) 100 ns

Clock delay time, t

d(clock)

(see Figure 2) 250 ns

Operating virtual junction temperature, T

(maximum to be calculated at worst case P

at 85°C ambient) −40 100 °C

(1)

It is understood that for V

I(3.3V)

< 3 V, voltages within the absolute maximum ratings applied to pin 5 V or pin 12 V will not damage the IC.

ELECTRICAL CHARACTERISTICS

= 25°C, V

I(5V)

= 5 V, V

I(3.3V)

= 3.3 V, V

I(12V)

= 12 V, all outputs unloaded (unless otherwise noted)

POWER SWITCH

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

3.3V to xVCC

(2)

= 750 mA each 85 110

3.3V to xVCC

(2)

= 750 mA each, T

= 100°C 110 140

mΩ

Static drain-

5V to xVCC

(2)

= 500 mA each 95 130

Ω

DS(on)

Static drain-

source on-state

5V to xVCC

(2)

= 500 mA each, T

= 100°C 120 160

DS(on)

source on-state

resistance

3.3V or 5V to xVPP

(2)

= 50 mA each 0.8 1

resistance

3.3V or 5V to xVPP

(2)

= 50 mA each, T

= 100°C 1 1.3

Ω

12V to xVPP

(2)

= 50 mA each 2 2.5

Ω

12V to xVPP

(2)

= 50 mA each, T

= 100°C 2.5 3.4

Output discharge

Discharge at xVCC I

O(disc)

= 1 mA 0.5 0.7 1

kΩ

Output discharge

resistance

Discharge at xVPP I

O(disc)

= 1 mA 0.2 0.4 0.5

Ω

Limit (steady-state value),

output powered into a short

OS(xVCC)

1 1.4 2 A

Short-circuit output current

output powered into a short

circuit

OS(xVPP)

120 200 300 mA

Short-circuit output current

Limit (steady-state value),

output powered into a short

OS(xVCC)

1 1.4 2 A

output powered into a short

circuit, T

= 100°C

OS(xVPP)

120 200 300 mA

Thermal shutdown

(2)

Thermal trip point, T

Rising temperature 135

°C

Thermal shutdown

temperature

(2)

Hysteresis, T

Current-limit response time

(3)(4)

5V to xVCC = 5 V, with 100-mΩ short to GND 10

Current-limit response time

(3)(4)

5V to xVPP = 5 V, with 100-mΩ short to GND 3

(1)

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

(2)

TPS2204A and TPS2206A: two switches on. TPS2210A: one switch on.

(3)

Specified by design; not tested in production.

(4)

From application of short to 110% of final current limit.







SLVS449A − DECEMBER 2002 − REVISED MAY 2003

www.ti.com

ELECTRICAL CHARACTERISTICS Continued

= 25°C, V

I(5V)

= 5 V, V

I(3.3V)

= 3.3 V, V

I(12V)

= 12 V, all outputs unloaded (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Normal

I(3.3V)

(xVCC) = V

(xVPP) = 3.3 V and

140 200

Normal

operation

I(5V)

(xVCC) = V

(xVPP) = 3.3 V and

also for RESET = 0 V

8 12

Input current,

operation

I(12V)

also for RESET = 0 V

100 180

Input current,

quiescent

Shutdown

I(3.3V)

0.3 2

quiescent

Shutdown

mode

I(5V)

(xVCC) = V

(xVPP) = Hi-Z

0.1 2

mode

I(12V)

(xVCC) = V

(xVPP) = Hi-Z

0.3 2

O(xVCC)

= 5 V,

lkg

Leakage current,

Shutdown mode

O(xVCC)

= 5 V,

I(5V)

= V

I(12V)

= 0 V

= 100°C 50

lkg

Leakage current,

output off state

Shutdown mode

O(xVPP)

= 12 V,

output off state

O(xVPP)

= 12 V,

I(5V)

= V

I(12V)

= 0 V

= 100°C 50

LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(RESET)

(1)

RESET = 5.5 V −1 1

I(RESET)

(1)

RESET = 0 V −30 −20 −10

I(SHDN)

(1)

SHDN = 5.5 V −1 1

Input current, logic

I(SHDN)

(1)

SHDN = 0 V −50 −3

µA

Input current, logic

I(LATCH)

(1)

LATCH = 5.5 V 50

µA

I(LATCH)

(1)

LATCH = 0 V −1 1

I(CLOCK,

DATA)

0 V to 5.5 V −1 1

High-level input voltage, logic 2 V

Low-level input voltage, logic 0.8 V

O(sat)

Output saturation voltage at OC I

= 2 mA 0.14 0.4 V

lkg

Leakage current at OC V

O(/OC)

= 5.5 V 0 1 µA

(1)

LATCH has low current pulldown. RESET and SHDN have low-current pullup.

UVLO AND POR (POWER-ON RESET)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(3.3V)

Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V

hys(3.3V)

UVLO hysteresis voltage at VA

(1)

100 mV

I(5V)

Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 2.9 V

hys(5V)

UVLO hysteresis voltage at 5 V

(1)

100 mV

Delay time for falling response, UVLO

(1)

Delay from voltage hit (step from 3 V to 2.3 V)

to Hi-Z control (90% V

to GND)

4 µs

I(POR)

Input voltage, power-on reset

(1)

3.3-V voltage below which POR is asserted

causing a RESET internally with all line

switches open and all discharge switches

closed.

1.7 V

(1)

Specified by design; not tested in production.







SLVS449A − DECEMBER 2002 − REVISED MAY 2003

www.ti.com

SWITCHING CHARACTERISTICS

= 5 V, T

= 25°C, V

I(3.3V)

= 3.3 V, V

I(5V)

= 5 V, V

I(12)

= 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted)

PARAMETER

(1)

LOAD CONDITION

TEST CONDITIONS

(2)

MIN TYP MAX UNIT

(3)

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

O(xVCC)

= 5 V 0.9

Output rise times

(3)

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

O(xVCC)

= 0 A, I

O(xVPP)

= 0 A

O(xVPP)

= 12 V 0.26

Output rise times

(3)

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

O(xVCC)

= 5 V 1.1

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

O(xVCC)

= 0.75 A, I

O(xVPP)

= 50 mA

O(xVPP)

= 12 V 0.6

(3)

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

O(xVCC)

= 5 V,

Discharge switches ON

0.5

Output fall times

(3)

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

O(xVCC)

= 0 A, I

O(xVPP)

= 0 A

O(xVPP)

= 12 V,

Discharge switches ON

0.2

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

O(xVCC)

= 5 V 2.35

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

O(xVCC)

= 0.75 A, I

O(xVPP)

= 50 mA

O(xVPP)

= 12 V 3.9

Latch↑ to xVPP (12 V)

pdon

Latch↑ to xVPP (12 V)

pdoff

0.62

Latch↑ to xVPP (5 V)

pdon

0.77

Latch

↑

to xVPP (5 V)

pdoff

0.51

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

Latch↑ to xVPP (3.3 V)

pdon

0.75

L(xVCC)

= 0.1 µF, C

L(xVPP)

= 0.1 µF,

O(xVCC)

= 0 A, I

O(xVPP)

= 0 A

Latch

↑

to xVPP (3.3 V)

pdoff

0.52

O(xVCC)

= 0 A, I

O(xVPP)

= 0 A

Latch↑ to xVCC (5 V)

pdon

0.3

Latch

↑

to xVCC (5 V)

pdoff

2.5

Latch↑ to xVCC (3.3V)

pdon

0.3

Propagation delay

(3)

Latch

↑

to xVCC (3.3V)

pdoff

2.8

Propagation delay

times

(3)

Latch↑ to xVPP (12 V)

pdon

2.2

times

Latch↑ to xVPP (12 V)

pdoff

0.8

Latch↑ to xVPP (5 V)

pdon

0.8

Latch

↑

to xVPP (5 V)

pdoff

0.6

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

Latch↑ to xVPP (3.3 V)

pdon

0.8

L(xVCC)

= 150 µF, C

L(xVPP)

= 10 µF,

O(xVCC)

= 0.75 A, I

O(xVPP)

= 50 mA

Latch

↑

to xVPP (3.3 V)

pdoff

0.6

O(xVCC)

= 0.75 A, I

O(xVPP)

= 50 mA

Latch↑ to xVCC (5 V)

pdon

0.6

Latch

↑

to xVCC (5 V)

pdoff

2.5

Latch↑ to xVCC (3.3V)

pdon

0.5

Latch

↑

to xVCC (3.3V)

pdoff

2.6

(1)

Refer to Parameter Measurement Information in Figure 1.

(2)

No card inserted, assumes a 0.1-µF output capacitor (see Figure 1).

(3)

Specified by design; not tested in production.

剩余31页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 3186
资源: 5482

TI-TPS2206A.pdf

TI-ADC32RF54.pdf

TI-TPS65983B.pdf

TI-UCC28710.pdf

TI-UCC28911.pdf

TI-SN7489J.pdf

TI-TPS2206.pdf

TI-TPS2214A.pdf

TI-TPS53317A.pdf

TI-TPS658610A.pdf

TI-UC27131.pdf

TI-CC3120.pdf

TI-LMP90080.pdf

TI-UCC24636.pdf

TI-AFE58JD16.pdf

TI-TPS658622A.pdf

TI-TPS65632A.pdf

TI-TPS65160A.pdf

TI-TPS65167A.pdf

TI-TPS65177A.pdf

TI-VCA8500.pdf

TI-LMH1219.pdf

TI-DRV8303.pdf

TI-OPA2391.pdf

TI-TPS92390.pdf

TI-TPS65642A.pdf

TI-TPS92314A.pdf

TI-TPS65563A.pdf

TI-TPS23753A.pdf

TI-TPS2211A.pdf

最新资源