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《TI-TPS2211A：单插槽PC卡电源接口开关》 TI-TPS2211A是一款专为单插槽PC卡设计的电源接口切换器，它集成了电源管理解决方案，旨在简化系统设计并提高可靠性。这款器件采用德州仪器的LinBiCMOS工艺，将所有离散的电源MOSFET、逻辑部分、电流限制和热保护功能整合在一个单片集成电路中。该芯片的主要特点包括： 1. **低rDS(on)**：拥有70毫欧的5V VCC开关和3.3V VCC开关，这意味着在开关操作时具有较低的导通电阻，从而减少了电源转换时的电压降，提高了效率。 2. **兼容性**：与行业标准控制器兼容，可以与多种PCMCIA控制器配合使用，确保了广泛的适用性。 3. **3.3V低压模式**：在3.3V低电压模式下工作，无需5V电源，这使得在只有3.3V可用的情况下（如睡眠模式或寻呼模式）仍能正常工作，非常适合低功耗系统设计。 4. **电源选择**：能够分配3.3V、5V或12V的卡电源，并且兼容3.3V、5V和12V的PC卡。 5. **短路和热保护**：内置短路保护和热保护机制，防止过流和过热导致的损坏，增强了系统的稳定性。 6. **节省空间的封装**：提供16引脚SSOP（DB）和20引脚HTSSOP（PWP）封装，减小了板级空间需求，适用于紧凑型设备设计。 7. **断开再连接切换**：采用断开再连接的切换方式，确保在电源切换过程中不会发生电源瞬态问题，提高了系统安全性。 TPS2211A的应用领域广泛，包括笔记本电脑、台式机、个人数字助手（PDA）、数码相机和条形码扫描器等设备。其封装选项有塑料小外形（DB和PW）以及带有PowerPAD的塑料小外形（PWP），工作温度范围为-40°C至85°C。 TI-TPS2211A是针对PC卡电源管理的一种高效解决方案，通过集成化设计减少了组件数量，提高了系统的可靠性和能效，同时提供了灵活的电源选择和保护功能，适应不同应用场景的需求。

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   

SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005

WWW.TI.COM

D Fully Integrated V

and V

Switching for

Single-Slot PC Card Interface

D Low r

DS(on)

(70-mΩ 5-V V

Switch and

3.3-V V

Switch)

D Compatible With Industry-Standard

Controllers

D 3.3-V Low-Voltage Mode

D Meets PC Card Standards

D 12-V Supply Can Be Disabled Except

During 12-V Flash Programming

D Short-Circuit and Thermal Protection

D Space-Saving 16-Pin SSOP (DB) and 20-Pin

HTSSOP (PWP)

D Compatible With 3.3-V, 5-V, and 12-V PC

Cards

D Break-Before-Make Switching

description

The TPS2211A PC Card power-interface switch

provides an integrated power-management solu-

tion for a single PC Card. All of the discrete power

MOSFETs, a logic section, current limiting, and

thermal protection for PC Card control are

combined on a single integrated circuit, using the

Texas Instruments LinBiCMOS process. The

circuit allows the distribution of 3.3-V, 5-V, and/or

12-V card power, and is compatible with many PCMCIA controllers.

The current-limiting feature eliminates the need for fuses, which reduces component count and

improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. controllers.

The current-limiting feature eliminates the need for fuses, which reduces component count and

improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card.

The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias

power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as

sleep mode and pager mode where only 3.3 V is available.

End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants

(PDAs), digital cameras, and bar-code scanners.

AVAILABLE OPTIONS

PACKAGED DEVICE

PLASTIC SMALL OUTLINE

(DB)

PLASTIC SMALL OUTLINE

(PW)

PowerPAD

PLASTIC SMALL OUTLINE

(PWP)

−40°C to 85°C

TPS2211AIDB

TPS2211APW TPS2211APWP

The DB, PW, and PWP packages are only available left-end taped and reeled (indicated by the R suffix on the device type,

e.g. TPS2211AIDBR).

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).

LinBiCMOS, PowerPAD are trademarks of Texas Instruments.

VCCD0

VCCD1

3.3V

GND

SHDN

VPPD0

VPPD1

AVCC

AVPP

12V

DB PACKAGE

†

(TOP VIEW)

†

TPS2211A is pin-for-pin compatible with TPS2211 and

TPS2212.

VCCD0

VCCD1

3.3 V

5 V

GND

12 V

SHDN

VPPD0

VPPD1

AVCC

AVPP

PW and PWP

PACKAGE

(TOP VIEW)

‡

NC − No internal connection

‡

Must be tied together externally as close to the device as

possible.

PowerPAD applies to PWP package only.

See Note

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     

   

SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005

WWW.TI.COM

Terminal Functions

TERMINAL

NAME

NO.

I/O DESCRIPTION

NAME

PW, PWP DB

I/O

DESCRIPTION

3.3V 3, 4 3, 4 I 3.3-V V

input for card power and/or chip power if 5 V is not present

5V 5, 6 5, 6 I 5-V V

input for card power and/or chip power

12V 10 9 I 12-V V

input card power

AVCC 13, 14, 15, 16 11, 12, 13 O

Switched output that delivers 0 V, 3.3-V, 5-V, or high impedance to card; must be tied together

externally for the 20-pin PWP package.

AVPP 11 10 O Switched output that delivers 0 V, 3.3-V, 5-V, 12-V, or high impedance to card

GND 8 7 Ground

NC 7, 12, 17 − No internal connection

OC 9 8 O Logic-level overcurrent reporting output that goes low when an overcurrent conditions exists

SHDN 20 16 I Logic input that shuts down the device and sets all power outputs to high-impedance state

VCCD0 1 1 I Logic input that controls voltage of AVCC (see control-logic table)

VCCD1 2 2 I Logic input that controls voltage of AVCC (see control-logic table)

VPPD0 19 15 I Logic input that controls voltage of AVPP (see control-logic table)

VPPD1 18 14 I Logic input that controls voltage of AVPP (see control-logic table)

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Input voltage range for card power: V

I(5V)

−0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(3.3V)

−0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(12V)

−0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic input voltage −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (each card): I

O(VCC)

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O(VPP)

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating

virtual junction temperature range, T

−40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

−40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE T

= 25°C

= 70°C

POWER RATING

= 85°C

POWER RATING

DB−16 800 mW 8.0 mW/°C 440 mW 320 mW

PW−20 741.3 mW 7.41 mW/°C 407.7 mW 296.5 mW

PWP−20 2740 mW 27.4 mW/°C 1507 mW 1096 mW

These devices are mounted on a Low-K PCB with 0 LFM.

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   

SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005

WWW.TI.COM

recommended operating conditions

MIN MAX UNIT

I(5V)

0 5.25 V

Input voltage, V

I(3.3V)

0 5.25 V

Input voltage, V

I(12V)

0 13.5 V

Output current

O(AVCC)

1 A

Output current

O(AVPP)

150 mA

Operating virtual junction temperature, T

−40 125 °C

electrical characteristics, T

= −40°C to 85°C (unless otherwise noted)

power switch

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX UNIT

5 V to AVCC V

I(5V)

= 5 V 70 120

mΩ

3.3 V to AVCC V

I(3.3V)

= 3.3 V 70 120

mΩ

Switch resistance

5 V to AVPP

= 25°C 4 6

Switch resistance

3.3 V to AVPP T

= 25°C 4 6

Ω

12 V to AVPP T

= 25°C 1 2

Ω

O(AVPP)

Clamp low voltage I

at 10 mA 0.3 0.8 V

O(AVCC)

Clamp low voltage I

at 10 mA 0.1 0.8 V

high-impedance state

= 25°C 1 10

lkg

Leakage current

high-impedance state

= 85°C 50

lkg

Leakage current

high-impedance state

= 25°C 1 10

µA

high-impedance state

= 85°C 50

I(5V)

= 5 V V

O(AVCC)

= 5 V, V

O(AVPP)

= 12 V 40 75

Input current

I(5V)

= 0 V,

I(3.3V)

= 3.3 V

O(AVCC)

= 3.3 V, V

O(AVPP)

= 12 V 50 90

µA

Shutdown mode V

O(AVCC)

= V

O(AVPP)

= Hi-Z 1

Short-circuit

O(AVCC)

= 85

C, output powered into a

1 2.5 A

Short-circuit

output-current limit

O(AVPP)

= 85 C, output powered into a

short to GND

180 400 mA

Thermal

shutdown

‡

Trip point, T

140 °C

Thermal

shutdown

‡

Hysteresis 10 °C

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

‡

Specified by design, not tested in production

logic section

PARAMETER

TEST CONDITIONS

†

MIN MAX UNIT

Logic input current 1 µA

Logic input high level 2 V

Logic input low level 0.8 V

Logic output high level, OC

I(5V)

= 5 V, I

= 0.2 mA V

I(5V)

− 0.4

Logic output high level, OC

I(5V)

= 0 V, I

= 0.2 mA, V

I(3.3V)

= 3.3 V V

I(3.3V)

− 0.4

Logic output low level, OC I

= 1 mA 0.4 V

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.



     

   

SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005

WWW.TI.COM

switching characteristics

‡

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

Rise times, output

O(AVCC)

(5 V) 2.8

Rise times, output

O(AVPP)

(12 V)

Fall times, output

O(AVCC)

(5 V) 5

Fall times, output

O(AVPP)

(12 V)

I(VPPD0)

to V

O(AVPP)

(12 V)

I(VPPD0)

to V

O(AVPP)

(12 V)

off

Propagation delay (see Figure1)

I(VCCD1)

to V

O(AVCC)

(3.3 V)

2.8

Propagation delay (see Figure1)

I(VCCD1)

to V

O(AVCC)

(3.3 V)

off

I(VCCD0)

to V

O(AVCC)

(5 V)

3.7

I(VCCD0)

to V

O(AVCC)

(5 V)

off

‡

Switching characteristics are with C

= 150 µF.

Refer to Parameter Measurement Information

PARAMETER MEASUREMENT INFORMATION

off

LOAD CIRCUIT

VOLTAGE WAVEFORMS

I(12V)

GND

50%

90%

GND

I(VPPD0)

O(AVPP)

AVPP

LOAD CIRCUIT

AVCC

VOLTAGE WAVEFORMS

I(3.3V)

GND

50%

90%

10%

GND

I(VCCD1)

O(AVCC)

10%

50%

I(VPPD1)

= 0 V)

I(VCCD0)

= V

)

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

FIGURE

AVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch 2

AVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch 3

AVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch 4

AVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch 5

AVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch 6

AVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch 7

AVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch 8

AVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch 9

AVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch 10

AVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch 11

AVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch 12

AVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch 13

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