TI-TLK106L.pdf资源-CSDN文库

需积分: 9 67 浏览量 2022-12-16 21:37:21 上传评论 3 收藏 1.48MB PDF 举报

资源推荐

资源详情

资源评论

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLK105L, TLK106L

SLLSEE3D –AUGUST 2013–REVISED APRIL 2016

TLK10xL Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

1 Device Overview

1.1 Features

• Low-Power Consumption:

– Single Supply: <205 mW PHY, 275 mW With

Center Tap (Typical)

– Dual Supplies: <126 mW PHY, 200 mW With

Center Tap (Typical)

• Programmable Power Back Off to Reduce PHY

Power up to 20% in Systems With Shorter Cables

• IEEE 1588 SFD Indication Enables Time Stamping

by a Controller or Processor

• Low Deterministic Latency Supports IEEE1588

Implementation

• Cable Diagnostics

• Programmable Fast Link Down Modes, <10 µs

Reaction Time

• Variable I/O voltage range: 3.3V, 2.5V, 1.8V

• MAC Interface I/O voltage range:

– MII I/O voltage range: 3.3V, 2.5V, 1.8V

– RMII I/O voltage range: 3.3V, 2.5V

• Fixed TX Clock to XI, With Programmable Phase

Shift

• Auto-MDIX for 10/100Mbs

• Energy Detection Mode

• MII and RMII Capabilities

• IEEE 802.3u MII

• Error-Free 100Base-T Operation up to 150 Meters

Under Typical Conditions

• Error-Free 10Base-T Operation up to 300 Meters

Under Typical Conditions

• Serial Management Interface

• IEEE 802.3u Auto-Negotiation and Parallel

Detection

• IEEE 802.3u ENDEC, 10Base-T

Transceivers and Filters

• IEEE 802.3u PCS, 100Base-TX Transceivers

• Integrated ANSI X3.263 Compliant TP-PMD

Physical Sublayer with Adaptive Equalization and

Baseline Wander Compensation

• Programmable LED Support Link, Activity

• 10/100Mbs Packet BIST (Built in Self Test)

• HBM ESD Protection on RD± and TD± of 16 kV

• 32-pin VQFN

(5 mm) × (5 mm)

1.2 Applications

• Industrial Networks and Factory Automation

• Motor and Motion Control

• General Embedded Applications

1.3 Description

The TLK10xL is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling, integrating all the

physical-layer functions needed to transmit and receive data on standard twisted-pair cables.

The device supports the standard Media Independent Interface (MII) and Reduced Media Independent

Interface (RMII) for direct connection to a Media Access Controller (MAC).

The device is designed for power-supply flexibility, and can operate with a single 3.3-V power supply or

with combinations of 3.3-V and 1.55-V power supplies for reduced power operation.

The TLK10xL uses mixed-signal processing to perform equalization, data recovery, and error correction to

achieve robust operation over CAT 5 twisted-pair wiring. The TLK10xL not only meets the requirements of

IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.

The TLK10xL Ethernet PHY has a special Power Back Off mode to conserve power in systems with

relatively short cables. This mode provides the flexibility to reduce system power when the system is not

required to drive the standard IEEE 802.3 100-m cable length, or the extended 150m, error-free cable

reach of the TLK10xL. For more detail, see application note SLLA328.

TLK105L, TLK106L

SLLSEE3D –AUGUST 2013–REVISED APRIL 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TLK105L TLK106L

Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 3

2 Revision History ........................................ 4

3 Pin Configuration and Functions..................... 7

3.1 Pin Diagram .......................................... 7

3.2 Serial Management Interface (SMI) .................. 8

3.3 MAC Data Interface .................................. 8

3.4 10Mbs and 100Mbs PMD Interface .................. 9

3.5 Clock Interface ....................................... 9

3.6 LED Interface......................................... 9

3.7 Reset and Power Down .............................. 9

3.8 Power and Bias Connections ....................... 10

4 Specifications........................................... 11

4.1 Absolute Maximum Ratings ........................ 11

4.2 ESD Ratings ........................................ 11

4.3 Recommended Operating Conditions .............. 11

4.5 TLK105L 32-Pin Industrial Device (85°C) Thermal

Characteristics....................................... 12

4.6 TLK106L 32-Pin Extended Temperature (105°C)

Device Thermal Characteristics..................... 12

4.7 DC Characteristics, VDD_IO ....................... 13

4.8 DC Characteristics ................................. 13

4.9 Power Supply Characteristics ....................... 14

4.10 AC Specifications.................................... 15

5 Detailed Description ................................... 31

5.1 Hardware Configuration ............................. 31

5.2 Architecture ......................................... 42

5.3 Register Maps ....................................... 51

6 Applications, Implementation, and Layout........ 90

6.1 Interfaces............................................ 90

6.2 Reset and Power-Down Operation.................. 99

6.3 Design Guidelines ................................. 101

7 Device and Documentation Support.............. 104

7.1 Documentation Support............................ 104

7.2 Related Links ...................................... 104

7.3 Community Resources............................. 104

7.4 Trademarks ........................................ 104

7.5 Electrostatic Discharge Caution ................... 104

7.6 Glossary............................................ 104

8 Mechanical Packaging and Orderable

Information............................................. 105

8.1 Packaging Information ............................. 105

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (November 2014) to Revision D Page

• Changed description of I/O Voltage Range and MAC interfaces to clarify voltages. ....................................... 1

• Changed QFN to VQFN ............................................................................................................. 1

• Added package information ......................................................................................................... 1

• Added note for oscillator voltage levels............................................................................................ 9

• Updated Handling Ratings to ESD Ratings and moved Storage temperature to Absolute Maximum Ratings ......... 11

• Added parameters for dual-supply operation.................................................................................... 11

• Changed Thermal Table format .................................................................................................. 12

• Added timing parameter for XI clock stability after power up. ................................................................ 15

• Deleted CLK25MHz_OUT.......................................................................................................... 34

• Added note on impact of enabling Enhanced LED link on link blinking...................................................... 36

• Changed format of table header. ................................................................................................. 44

• Added note that the default transmit link pulse polarity is reversed .......................................................... 48

• Changed Register Block to Register Maps ..................................................................................... 51

• Added Compliance Test register. ................................................................................................ 52

• Changed format of Register Table header row. ................................................................................ 53

• Changed format of Register Table header row. ................................................................................ 54

• Changed VRCR bits 3:0 to RESERVED. ........................................................................................ 55

• Changed Speed Selection register bit to RW ................................................................................... 56

• Changed Auto-Negotiation Enable register bit to RW.......................................................................... 56

• Added Reserved bits................................................................................................................ 67

• Added note that enabling Enhanced LED Link overrides the LED blinking functionality of PHYCR register bit 5 ..... 67

• Changed default to inverted polarity ............................................................................................. 68

• Added text in MLEDCR clarifying polarity of LED. ............................................................................. 81

• Added Compliance Test register, address 0x0027 ............................................................................ 82

• Changed Power Back Off Levels ................................................................................................. 83

• Changed VRCR bits 3:0 to RESERVED ........................................................................................ 84

TLK105L, TLK106L

www.ti.com

SLLSEE3D –AUGUST 2013–REVISED APRIL 2016

Submit Documentation Feedback

Product Folder Links: TLK105L TLK106L

• Changed "the same levels as the MII interface" to "operates at 3.3V or 2.5V VDD_IO levels" .......................... 92

• Deleted partial list of recommended transformers ............................................................................ 101

• Changed recommendation for common mode chokes to requirement. .................................................... 101

• Deleted the amplitude of the oscillator should be a nominal voltage of 3.3V. ............................................ 101

• Added notes on oscillator supply voltage....................................................................................... 101

Changes from Revision B (January 2014) to Revision C Page

• Deleted "(TLK106)" ................................................................................................................... 1

• Deleted "IEEE 802.3u 100BASE-FX Fiber Interface"............................................................................ 1

• Deleted "Additionally, the TLK10xL supports 100Base-FX signaling via an external optical transceiver." ............... 1

• Deleted "SD_IN" ...................................................................................................................... 9

• Deleted Redundant row "Power dissipation 200 mW" ......................................................................... 11

• Deleted DC Characteristics, SD_IN............................................................................................... 13

• V

TH1

- max value deleted, 200-mV typ value added ............................................................................ 13

• Deleted FX Timing .................................................................................................................. 18

• Deleted 25MHz_OUT Clock Timing .............................................................................................. 30

• Deleted FIBCR Register............................................................................................................ 52

• Deleted Fiber Mode Control 2 and Fiber Mode Control 3...................................................................... 52

• Deleted Fiber Mode Control ....................................................................................................... 53

• Deleted Fiber Mode Control Register, Fiber Mode Control 2 and Fiber Mode Control 3 .................................. 55

• Deleted Bit[14] Fiber Mode Control ............................................................................................... 67

• Changed "Active WOL" to "Active Energy Saving " ............................................................................. 72

• Changed "Passive WOL" to "Passive Energy Saving" ......................................................................... 72

• Changed "1" to "0" .................................................................................................................. 81

• Deleted Fiber Mode Control Register (FIBCR).................................................................................. 83

• Deleted Fiber Mode Control Register 2 (FIBCR2) .............................................................................. 84

• Deleted Fiber Mode Control Register 3 (FIBCR3) .............................................................................. 84

• Changed "WOL (Wake-On LAN)" to "Energy Saving" ........................................................................ 100

Changes from Revision A (November 2013) to Revision B Page

• Changed "Low Power Consumption: <205mW PHY and 275mW with Center Tap (Typical)" to "Low Power

Consumption: <126mW PHY and 200mW with Center Tap (Typical, dual supplies)"....................................... 1

• Changed "MII and RMII Interfaces" to "MII and RMII Capabilities" ............................................................ 1

• Changed "Error-Free Operation up to 150 Meters Under Typical Conditions" to " Error-Free 100Base-T

Operation up to 150 Meters Under Typical Conditions Error-Free 10Base-T Operation up to 300 Meters Under

Typical Conditions" ................................................................................................................... 1

• Added operating conditions for single and dual supplies ...................................................................... 11

• Changed title from "Active Power" to "Active Power, Single Supply Operation"............................................ 14

• Added Dual Supply Operation table .............................................................................................. 14

• Added bit 10, Fast Link Down Mode enable, Drop the link based on descrambler link loss, adusted description

of bits 3:0 to reflect 5 options instead of 4 ....................................................................................... 68

• Deleted " Allow the system to reset the PHY using register access."........................................................ 81

• Changed recommended transformer from Pulse HX1188 to Pulse HX1198 .............................................. 101

Changes from Original (August 2013) to Revision A Page

• Updated Pin Layout, changed "VDD33_IO" to "VDD_IO" ....................................................................... 7

• Added maximum storage temperature ........................................................................................... 11

• Changed "... stable for minimum of 1ms ..." to "... stable for minimum of 1µs ..." (typo correction)...................... 15

• Changed titles, "100Base-TX ... Timing" to "100Base-TX / FX ... Timing" .................................................. 18

• Added Power Back Off Control Register (0AEh)................................................................................ 51

• Registers 0010h - 001Fh moved from extended-addressing space to direct-addressing space ......................... 56

• Changed default value for MDL_REV from 0001 to 0010 ..................................................................... 59

• Changed Default value of interrupt-polarity bit from 0 to 1 ................................................................... 72

• Updated RMII Control and Status Register bit 4 description .................................................................. 77

剩余109页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 3194
资源: 5518

TI-TLK106L.pdf

TI-ADC32RF54.pdf

TI-UCC28911.pdf

TI-UCC24636.pdf

TI-SN7489J.pdf

TI-AFE58JD16.pdf

TI-TLK106.pdf

TI-TLK6201EA.pdf

TI-TLK1102E.pdf

TI-TLK2201BI.pdf

TI-UCC28710.pdf

TI-VCA8500.pdf

TI-UC27131.pdf

TI-CC3120.pdf

TI-DRV8303.pdf

TI-TLK1002A.pdf

TI-TLK1101E.pdf

TI-TLK110.pdf

TI-TLK1211.pdf

TI-TLK111.pdf

TI-LMH1219.pdf

TI-OPA2391.pdf

TI-TPS92390.pdf

TI-TPS65983B.pdf

TI-LMP90080.pdf

TI-TLK1221.pdf

TI-TLK100.pdf

TI-TLK2226.pdf

前端开源库-tlk-lexer

SOM-TLK7核心板规格书

最新资源