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FEATURES

FUNCTIONAL OVERVIEW

TLK2226

SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006

6 PORT GIGABIT ETHERNET TRANSCEIVER

• Standard Parallel Interface Timing:

• Six 1.25 Gigabits Per Second (Gbps) – Source Centered/Aligned Timing on Inputs

Synchronizable Transceivers (Support for 100

– Source Centered/Aligned Timing on

Mbps 100Base-FX Mode)

Outputs

• Configurable 1, 2, 3, 4, 5, or 6 Port Operation

• Comprehensive Suite Of Built-In Testability

via MDIO

• IEEE 802.3 Clause 22 Management Data

• Low Power Consumption <1.5W at 1.25Gb/sec

Interface (MDIO) Support

• IEEE 802.3z Gigabit Ethernet Compliant

• IEEE 1149.1 JTAG Support

• Differential VML Transmit Outputs With no

• Hot Plug Protection on Serial I/O

External Components Necessary

• No External Filter Components Required for

• Programmable High Speed Output

PLLs

Pre-Emphasis Levels

• Small Footprint 15 × 15 mm, 196-Pin, 1,0 mm

• Nibble Wide RTBI/RGMII Compliant Interface

Ball Pitch BGA

• Selectable Clock Tolerance Compensation

• Advanced Low Power 0.18 µ m CMOS

• Selectable on Chip Physical Coding Sublayer Technology

(PCS) Functions Including 8b/10b IEEE 802.3z

• Commercial Temperature Rating (0 ° C to 70 ° C)

Compliant Encoder and Decoder

• Repeater Mode:

• 1/10

Rate Capability for 125 Mbps Operation

– In the Serial Domain Using Recovered

With Automatic Rate Sense Capability

Clock (Non-Retiming)

• JEDEC 1.5V HSTL (Extendable to 1.8 V) on

– In the Parallel Domain Using REFCLK

Parallel Data Busses

(Retiming)

• JEDEC 1.8/2.5/3.3 V LVCMOS on REFCLK and

• Jumbo Packet (9300 Byte) Support

Control Pins

• Clause 36A Test Pattern Gen/Ver

• Internal Series Termination on HSTL Outputs

• SGMII Mode Support (10/100/1000 Mbps)

to Drive 50 Ω Lines

• Parallel Port Swap Mode

The TLK2226 is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high

port density and ultra-low power in a small form factor footprint. The TLK2226 provides for high-speed

full-duplex point-to-point data transmissions based on the IEEE802.3z 1000Mbps Ethernet specification. The

TLK2226 supports data rates from 1.0 Gbps through 1.3 Gbps. Each channel is capable of operating at 125

Mbps for IEEE Ethernet 100FX mode, and the rate for each channel may be set through MDIO or automatically

sensed and set by the TLK2226.The primary application of this device is to provide building blocks for

developing point-to-point baseband data transmission over controlled impedance media of 50 Ω . The

transmission media can be printed circuit board traces, copper cables or fiber-optical media. The ultimate rate

and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise

coupling to the environment.

This device performs the data encoding, decoding, serialization, deserialization, clock extraction and clock

tolerance compensation functions for a physical layer interface device. Each channel operates at up to 1.3 Gbps

providing up to 7.5 Gbps of aggregate data bandwidth over a copper or optical media interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

www.ti.com

TLK2226

SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006

The TLK2226 has six channels of SERDES each with 5 bit busses clocked double data rate (DDR). The parallel

interface accepts un-encoded or 5-bit wide encoded data aligned to both the rising and falling edge of the

transmit clock. The data is clocked low-order bits first, (i.e. bits 0–4 of the 8b/10b encoded data) on the rising

edge of the transmit clock and the high-order bits (i.e. bits 5–9 of the 8b/10b encoded data) are clocked on the

falling edge of the clock. The receive path interface is clocked in the same manner.

The TLK2226 supports two modes that can repeat data from a channel’s serial receiver to the adjacent

channel’s serial transmitter: serial repeater mode and retiming repeater mode. In serial repeater mode, the

clock/data recovery (CDR) function will lock onto the incoming data stream and will pass this data stream over to

the adjacent channel to be retransmitted. In serial repeater mode, the data stream stays in the same clock

domain as the incoming data; there is no clock tolerance compensation function performed to align the data

stream to the reference clock domain. In retiming repeater mode, the CDR function will lock onto the incoming

data stream but the data will be deserialized and passed through the CTC FIFO and then serialized for

transmission on the adjacent channel. In both repeater modes, the received data for Channel A is retransmitted

on the output for channel B while the received data for Channel B is retransmitted on the output for Channel A.

Likewise, Channel C is paired with Channel D, and Channel E is paired with Channel F. The repeater modes

can be enabled on a channel by channel basis through the use of register control bits programmed through the

MDIO interface.

The recovered data clock frequency can be aligned to the reference clock on each channel by means of a clock

tolerance compensation circuit and internal FIFO that will insert or drop Idle 20-bit IDLE codes as needed in the

absence of data. The received data for all channels are aligned to a single receive data clock that is a buffered

version of the reference clock.

The TLK2226 supports a selectable IEEE802.3z compliant 8b/10b encoder/decoder in all its 1.25Gbps modes of

operation, and a IEEE802 compliant 4b/5b encoder/decoder in its 125Mbps mode of operation.

The TLK2226 supports selectable RTBI and RGMII interface to supervision ASIC.

The TLK2226 automatically locks onto incoming data without the need to pre-lock.

Detection of whether the incoming data stream is at 1.25 Gbps or 125 Mbps data rate is automatic.

A comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and

verification is provided. An IEEE 1149.1 JTAG port is also supported to aid in board manufacturing test.

This device is housed in a small form factor 15 × 15 mm, 196-pin, BGA with 1,0 mm ball pitch and is

characterized to support the commercial temperature range of 0 ° C to 70 ° C.

Expect the TLK2226 to consume less than 1.5 W, when operating at 1.25 Gbps.

The TLK2226 is designed to be hot plug capable. A power-on reset puts the parallel side output signal pins in a

high-impedance state during power-up as well as pulls both TX+ and TX– to VDDA through 500 Ω .

Submit Documentation Feedback

www.ti.com

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

LVCMOS ELECTRICAL CHARACTERISTICS

(1)

TLK2226

SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE UNIT

DDQ

I/O Supply voltage

(2)

–0.3 to 2.5 V

DDS

I/O Supply voltage

(2)

–0.3 to 3.6 V

, V

DDA

Core Supply voltage

(2)

–0.3 to 2.5 V

LVCMOS –0.5 to 3.6

Input voltage V

HSTL –0.5 to 2.5

DC Input voltage (I/O ) –0.3 to 2.5 V

Storage temperature –65 to 85 ° C

Electrostatic discharge HBM: 2KV, CDM:750 V

Characterized free-air operating temperature range 0 to 70 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal

MIN NOM MAX UNIT

Peak-peak AC noise in the 1–10 MHz range may not

Core supply voltage 1.7 1.8 1.9 V

exceed 100 mV

1.5 V HSTL Class 1 peak-peak AC noise may not

1.4 1.5 1.6 V

exceed 150 mV

DDQ

HSTL I/O supply voltage

1.8 V HSTL Class 1 peak-peak AC noise may not

1.7 1.8 1.9 V

exceed 150 mV

1.8 V CMOS peak-peak AC noise may not exceed 150

1.7 1.8 1.9 V

2.5 V CMOS peak-peak AC noise may not exceed 150

DDS

LVCMOS I/O supply voltage 2.375 2.5 2.625 V

3.3 V CMOS peak-peak AC noise may not exceed 150

3.14 3.3 3.47 V

Peak-peak AC noise in the 1–10 MHz range may not

DDA

Analog supply voltage 1.7 1.8 1.9 V

exceed 100 mV

1.5 V HSTL Class 1 0.7 0.75 0.8

REF

Input reference voltage

(1)

1.8 V HSTL Class 1 0.85 0.9 0.95

Core supply current R

= 125 MHz, V

= 1.8 V 390 mA

= 125 MHz, V

DDQ

= 1.5 V 146

_HSTL

HSTL I/O supply current mA

= 125 MHz, V

DDQ

= 1.8 V 204

= 125 MHz, V

DDS

= 1.8 V 1

DDS

LVCMOS I/O supply current R

= 125 MHz, V

DDS

= 2.5 V 3 mA

= 125 MHz, V

DDS

= 3.3 V 7

DDA

Analog supply current R

= 125 MHz, V

DDA

= 1.8 V 183 mA

Total power consumption R

= 125 MHz, V

DDQ

= 1.8 V 1.50 W

DDQ

Shutdown current ENABLE = low 30 mA

(1) Typically, the value of VREF is expected to be 0.5 V

DDQ

of the transmitting device and V

REF

is expected to track variations in V

DDQ

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage I

= –400 µ A, V

DDS

= MIN V

DDS

– 0.2 V

DDS

(1) Unused inputs that do not hold an integrated pull up or pull down circuit need to be terminated to either GND or VDDQ respectively to

avoid extensive currents and life time degradation.

Submit Documentation Feedback

www.ti.com

HSTL ELECTRICAL CHARACTERISTICS

REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)

(1)

TLK2226

SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006

LVCMOS ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-level output voltage I

= 1 mA, V

DDS

= MIN 0 0.25 0.5 V

DDS

= 1.8 V 1.4 V

DDS

+0.2

High-level input voltage V

DDS

= 2.5 V 1.55 V

DDS

+0.2 V

DDS

= 3.3 V 2.0 V

DDS

+0.2

DDS

= 1.8 V –0.2 0.63

Low-level input voltage V

DDS

= 2.5 V –0.2 0.7 V

DDS

= 3.3 V –0.2 1.4

High input current V

DDS

= MAX, V

= 2.0 V 400 µ A

Low input current V

DDS

= MAX, V

= 2.0 V –600 µ A

Input capacitance 4 pF

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OH(dc)

High-level output voltage DC output, logic high V

DDQ

–0.4 V

DDQ

OL(dc)

Low-level output voltage DC output, logic low 0.4 V

IH(dc)

High-level input voltage DC input, logic high V

REF

+0.10 V

DDQ

+0.3 V

IL(dc)

Low-level input voltage DC input, logic low –0.5 V

REF

–0.10 V

AC input, logic high, V

DDQ

= 1.5 V V

REF

+0.20

IH(ac)

High-level input voltage V

AC input, logic high, V

DDQ

= 1.8 V V

REF

+0.35

AC input, logic low, V

DDQ

= 1.5 V V

REF

–0.20

IL(ac)

Low-level input voltage V

AC input, logic low, V

DDQ

= 1.8 V V

REF

–0.35

High input current

Receiver only ± 10 µ A

Low input current

OH(dc)

High output current V

DDQ

= 1.5 V –8 mA

OL(dc)

Low output current V

DDQ

= 1.5 V 8 mA

Input capacitance 4 pF

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Minimum data rate TYP–0.01% 125 TYP+0.01% MHz

Frequency

Maximum data rate TYP–0.01% 125 TYP+0.01% MHz

Accuracy –100 100 ppm

Duty cycle 40% 50% 60%

Jitter Random and deterministic 40 ps

(1) This clock should be crystal referenced to meet the requirements of this table ( Contact TI for specific clocking recommendations). Rate

activity of REFCLK is internally monitored. As soon as REFCLK is disconnected the device will initiate a global power-down mode; PLLs

will be turned off, output divers disabled and other current sources such as pull-up’s and pull down’s will be disabled to avoid power

consumption. To re-activate the device, restart REFCLK.

Submit Documentation Feedback

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