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TLK111
SLLSEF8C –AUGUST 2013–REVISED NOVEMBER 2014
TLK111 PHYTER
®
Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver
1 Introduction
1.1 Features
1
• Fully Pin Compatible with the TLK110 Device • Error-Free 100Base-T Operation up to 150 Meters
Under Typical Conditions
• Low Power Consumption:
• Error-Free 10Base-T Operation up to 300 Meters
– Single Supply: <205mW PHY, 275mW with
Under Typical Conditions
Center Tap (Typical)
• Serial Management Interface
– Dual Supplies: <126mW PHY, 200mW with
Center Tap (Typical) • IEEE 802.3u ENDEC, 10Base-T
Transceivers and Filters
• Programmable Power Back Off to reduce PHY
power up to 20% in systems with shorter cables • IEEE 802.3u PCS, 100Base-TX Transceivers
• IEEE 1588 SFD indication enables time stamping • IEEE 1149.1 JTAG
by a controller or processor
• Integrated ANSI X3.263 Compliant TP-PMD
• Low deterministic latency supports IEEE1588 Physical Sublayer with Adaptive Equalization and
implementation Baseline Wander Compensation
• Cable Diagnostics • Programmable LED Support Link, 10/100Mbs
Mode, Activity, and Collision Detect
• Programmable Fast Link Down Modes, <10µs
reaction time • 10/100Mbs Packet BIST (Built in Self Test)
• Variable I/O voltage range: 1.8V to 3.3V • HBM ESD protection on RD± and TD± of 16kV
• 3.3-V MAC Interface • 48-pin LQFP Package (7mm) × (7mm)
• Fixed TX Clock to XI, with programmable phase
shift
• Auto-MDIX for 10/100Mbs
• Energy Detection Mode
• 25 MHz Clock Out
• MII and RMII Capabilities
• IEEE 802.3u MII
• IEEE 802.3u Auto-Negotiation and Parallel
Detection
1.2 Applications
• Industrial Networks and Factory Automation • Motor and Motion Control
• Real Time Industrial Ethernet Applications such as • General Embedded Applications
EtherCAT
®
, Ethernet/IP™, ProfiNET
®
, and
SERCOSIII
1.3 Description
The TLK111 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates
all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables.
The TLK111 supports the standard Media Independent Interface (MII) and Reduced Media Independent
Interface (RMII) for direct connection to a Media Access Controller (MAC).
The TLK111 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or
with combinations of 3.3V and 1.55V power supplies for reduced power operation.
The TLK111 uses mixed-signal processing to perform equalization, data recovery, and error correction to
achieve robust operation over CAT 5 twisted-pair wiring. This device not only meets the requirements of
IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MII Option
RMII Option
MII/RMII Interface
100BASE-T100BASE-T
TLK111
10BASE-T
or
100BASE-TX
Status
LEDs
TLK111
SLLSEF8C –AUGUST 2013–REVISED NOVEMBER 2014
www.ti.com
The TLK111 Ethernet PHY has a special Power Back Off mode to conserve power in systems with
relatively short cables. This mode provides the flexibility to reduce system power when the system is not
required to drive the standard IEEE 802.3 100m cable length, or the extended 150m, error-free cable
reach of the TLK111. For more detail, see application note SLLA328.
1.4 Functional Block Diagrams
Figure 1-1. TLK111 Functional Block Diagram
2 Introduction Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK111
TLK111
www.ti.com
SLLSEF8C –AUGUST 2013–REVISED NOVEMBER 2014
Table of Contents
1 Introduction ............................................... 1 5.4 Auto Negotiation..................................... 33
1.1 Features .............................................. 1 5.5 Link Down Functionality............................. 35
1.2 Applications........................................... 1 5.6 IEEE 1588 Precision Timing Protocol Support...... 36
1.3 Description............................................ 1 6 Reset and Power Down Operation.................. 37
1.4 Functional Block Diagrams ........................... 2 6.1 Hardware Reset..................................... 37
2 Pin Descriptions ......................................... 4 6.2 Software Reset...................................... 37
2.1 Pin Layout ............................................ 4 6.3 Power Down/Interrupt ............................... 37
2.2 Serial Management Interface (SMI) .................. 5 6.4 Power Save Modes ................................. 38
2.3 MAC Data Interface .................................. 5 7 Design Guidelines...................................... 39
2.4 10Mbs and 100Mbs PMD Interface .................. 6 7.1 TPI Network Circuit ................................. 39
2.5 Clock Interface ....................................... 6 7.2 Clock In (XI) Requirements ......................... 39
2.6 LED Interface......................................... 6 7.3 Thermal Vias Recommendation .................... 41
2.7 JTAG Interface ....................................... 6 8 Register Block .......................................... 42
2.8 Reset and Power Down .............................. 7 8.1 Register Definition................................... 47
2.9 Power and Bias Connections......................... 7 8.2 Cable Diagnostic Control Register (CDCR)......... 71
3 Hardware Configuration................................ 7 8.3 PHY Reset Control Register (PHYRCR)............ 72
3.1 Bootstrap Configuration .............................. 8 8.4 Multi LED Control register (MLEDCR) .............. 72
3.2 Power Supply Configuration .......................... 9 8.5 IEEE1588 Precision Timing Pin Select (PTPPSEL) 72
8.6 IEEE1588 Precision Timing Configuration
3.3 IO Pins Hi-Z State During Reset .................... 11
(PTPCFG) ........................................... 73
3.4 Auto-Negotiation .................................... 11
8.7 TX_CLK Phase Shift Register (TXCPSR) .......... 73
3.5 Auto-MDIX........................................... 12
8.8 Power Back Off Control Register (PWRBOCR) .... 73
3.6 PHY Address........................................ 12
8.9 Voltage Regulator Control Register (VRCR)........ 74
3.7 MII Isolate Mode .................................... 13
8.10 Cable Diagnostic Configuration/Result Registers ... 74
3.8 Software Strapping Mode ........................... 13
9 Electrical Specifications .............................. 80
3.9 LED Interface ....................................... 15
9.1 Absolute Maximum Ratings ........................ 80
3.10 Multi-Configurable LED (MLED) .................... 16
9.2 Handling Ratings .................................... 80
3.11 Loopback Functionality.............................. 16
9.3 Recommended Operating Conditions .............. 80
3.12 BIST ................................................. 18
9.4 48-Pin Industrial Device Thermal Characteristics... 81
3.13 Cable Diagnostics ................................... 19
9.5 48-Pin Extended Temperature (125°C) Device
4 Interfaces ................................................ 20
Thermal Characteristics............................. 81
4.1 Media Independent Interface (MII) .................. 20
9.6 DC Characteristics, VDD_IO ....................... 81
4.2 Reduced Media Independent Interface (RMII)...... 20
9.7 DC Characteristics ................................. 81
4.3 Serial Management Interface ....................... 23
9.8 Power Supply Characteristics ....................... 82
5 Architecture ............................................. 27
9.9 AC Specifications.................................... 83
5.1 100Base-TX Transmit Path ......................... 27
10 Revision History, Revision A ........................ 98
5.2 100Base-TX Receive Path ......................... 30
11 Revision History, Revision B ........................ 98
5.3 10Base-T Receive Path ............................. 32
12 Revision History, Revision C ........................ 98
Copyright © 2013–2014, Texas Instruments Incorporated Table of Contents 3
Submit Documentation Feedback
Product Folder Links: TLK111
DGND
IOGND
XI
XO
VDD_IO
MDC
MDIO
LED_LINK/AN_0
LED_SPEED / AN_1
LED_ACT / COL / AN_EN
CLK_OUT
RBIAS
PFBOUT
AVDD33
SW_STRAP
RESERVED
AGND
PFBIN1
TD +
TD –
AGND
RD +
RD –
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
INT PWDN
/
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_
TRST
JTAG_TDI
1
2
3
4
5
6
7
8
9
10
11
38
39
40
41
42
43
44
45
46
47
48
35
34
33
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
15
14
13
PFBIN2
RX_CLK
RX_DV / MII_MODE
CRS/CRS_DV / LED_CFG
RX_ER / AMDIX_EN
COL / PHYAD0
RXD_0 / PHYAD1
RXD_1 / PHYAD2
RXD_2 / PHYAD3
RXD_3 / PHYAD4
IOGND
VDD_IO
24
37
36
12
RESET
TLK111
SLLSEF8C –AUGUST 2013–REVISED NOVEMBER 2014
www.ti.com
2 Pin Descriptions
The TLK111 pins fall into the following interface categories (subsequent sections describe each interface):
• Serial Management Interface • Reset and Power Down
• MAC Data Interface • Bootstrap Configuration Inputs
• Clock Interface • 10/100Mbs PMD Interface
• LED Interface • Special Connect Pins
• JTAG Interface • Power and Ground pins
Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I Input Type: OD Open Drain
Type: O Output Type: PD, PU Internal Pulldown/Pullup
Type: I/O Input/Output Type: S Configuration Pin (All configuration pins have weak internal
pullups or pulldowns. Use an external 2.2kΩ resistor if you
need a different default value. See Section 3.1 for details.)
2.1 Pin Layout
Figure 2-1. TLK111 PIN DIAGRAM, TOP VIEW
This document describes signals that take on different names depending on configuration. In such cases,
the different names are placed together and separated by slash (/) characters. For example, "RXD_3 /
PHYAD4". Active low signals are represented by overbars.
.
4 Pin Descriptions Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK111
TLK111
www.ti.com
SLLSEF8C –AUGUST 2013–REVISED NOVEMBER 2014
2.2 Serial Management Interface (SMI)
PIN
TYPE DESCRIPTION
NAME NO.
MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The
MDC 31 I maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the
TX_CLK or the RX_CLK.
MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local
MDIO 30 I/O
controller or the TLK111 may drive the MDIO signal. This pin requires a pull-up resistor with value 2.2kΩ.
2.3 MAC Data Interface
PIN
TYPE DESCRIPTION
NAME NO.
MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock
depending on the speed. Note that in MII mode, this clock has constant phase referenced to
TX_CLK 1 O, PD REF_CLK. Applications requiring such constant phase may use this feature.
Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and
receive.
TRANSMIT ENABLE: TX_EN is presented on the rising edge of the TX_CLK . TX_EN
TX_EN 2 I, PD indicates the presence of valid data inputs on TXD[3:0] in MII mode, and on TXD [1:0] in the
RMII mode. TX_EN is an active high signal.
TXD_0 3
TRANSMIT DATA: In MII mode, the transmit data nibble received from the MAC is
TXD_1 4
I, PD synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] received from
TXD_2 5
the MAC is synchronous to the 50MHz reference clock on XI.
TXD_3 6
RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz
RX_CLK 38 O
reference clock, depending on the speed, that is derived from the received data stream.
RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode
RX_DV / MII_MODE 39 S, O, PD
or on RXD [1:0] for RMII mode, independently from Carrier Sense.
RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received
packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to
RX_ER / AMDIX_EN 41 S, O, PU
RX_CLK and in RMII mode, synchronously to XI (50MHz). This pin is not required to be used
by the MAC, in either MII or RMII, because the PHY is corrupting data on a receive error.
RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins
synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0]
RXD_0 / PHYAD1 43
is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode.
RXD_1 / PHYAD2 44
S, O, PD
RXD_2 / PHYAD3 45 PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0
RXD_3 / PHYAD4 46 (LSB of the address) is multiplexed with COL on pin 42, and is pulled up.
If no external pullup/pulldown is present, the default address is 0x01.
CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle.
CRS / LED_CFG 40 S, O, PU
CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier
and Receive Data Valid indications.
COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base-
COL / PHYAD0 42 S, O, PU
T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and
receive media are non-idle. This pin is not used in RMII mode.
Copyright © 2013–2014, Texas Instruments Incorporated Pin Descriptions 5
Submit Documentation Feedback
Product Folder Links: TLK111
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