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TI-TLK100.pdf
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Magnetics
MPU/CPU
Media AccessController
MII
10/100Mb/s
TLK100
25-MHz
Clock
Source
Status
LEDs
RJ-45
10BASE-T
or
100BASE-TX
B0312-01
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
Check for Samples: TLK100
1 Introduction
1.1 Features
1
• Temperature From –40°C to 85°C • Bus I/O Protection - ±16kV JEDEC HBM
• Low Power Consumption, < 200mW Typical • IEEE 802.3u PCS, 100BASE-TX Transceivers
• Cable Diagnostics • Enables IEEE1588 Time-Stamping
• Error-Free Operation up to 200 Meters Under • IEEE 1149.1 JTAG
Typical Conditions
• Integrated ANSI X3.263 Compliant TP-PMD
• 3.3V MAC Interface Physical Sublayer with Adaptive Equalization
and Baseline Wander Compensation
• Auto-MDIX for 10/100 Mb/s
• Programmable LED Support Link, 10/100 Mb/s
• Energy Detection Mode
Mode, Activity, and Collision Detect
• 25 MHz Clock Out
• 10/100 Mb/s Packet BIST (Built in Self Test)
• MII Serial Management Interface (MDC and
• 48-pin TQFP Package (7mm) × (7mm)
MDIO)
• IEEE 802.3u MII
1.2 Applications
• IEEE 802.3u Auto-Negotiation and Parallel
Detection
• Industrial Controls and Factory Automation
• IEEE 802.3u ENDEC, 10BASE-T
• General Embedded Applications
Transceivers and Filters
1.3 General Description
The TLK100 is a single-port Ethernet PHY for 10BaseT and 100Base TX signaling. It integrates all the
physical-layer functions needed to transmit and receive data on standard twisted-pair cables. This device
supports the standard Media Independent Interface (MII) for direct connection to a Media Access
Controller (MAC).
The TLK100 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or
with combinations of 3.3V, 1.8V, and 1.1V power supplies for reduced power operation.
The TLK100 uses mixed-signal processing to perform equalization, data recovery, and error correction to
achieve robust operation over CAT 5 twisted-pair wiring. It not only meets the requirements of IEEE 802.3,
but maintains high margins in terms of cross-talk and alien noise.
1.4 System Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TX_CLK
TXD[3:0]
TX_EN
MDIO
MDC
COL
CRS/CRS_DV
RX_ER
RX_DV
RXD[3:0]
RX_CLK
TX_DATA RX_CLK
Referen
c
e Clock
TD± RD± LEDs
MII Interface
Auto-MDIX
DAC ADC
JTAG
MII
Serial
Management
TX_CLK RX_DATA
10BASE-T
and
100BASE-TX
10BASE-T
and
100BASE-TX
Transmit
Block
Receive
Block
MII
Registers
Auto-Negotiation
StateMachine
Clock
Generation
Boundary
Scan
LED
Drivers
B0313-01
Cable
Diagnostics
BIST
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
Figure 1-1. TLK100 Functional Block Diagram
2 Introduction Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLK100
VSS
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
TLK100
RBIAS
CLK25OUT
MII_TXD_0
MII_TXD_1
MII_TXD_2
MII_TXD_3
MII_RX_CLK
MII_CRS / LED_CFG
MII_TX_EN
MII_TX_CLK
MII_COL / PHYAD0
MII_RX_DV
MII_RXD_0 / PHYAD1
MII_RXD_1 / PHYAD2
MII_RXD_2 / PHYAD3
MII_RXD_3 / PHYAD4
MDC
MDIO
LED_ACT / AN_EN
LED_SPEED / AN_1
LED_LINK / AN_0
PWRDNN/INT
RESETN
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRSTN
XO
MII_RX_ERR / MDIX_EN
TD-
TD+
RD-
RD+
VA11_PFBOUT
V18_PFBOUT
VA11_PFBIN1
VA11_PFBIN2
V18_PFBIN1
V18_PFBIN2
VDD33_VA11
VDD11
VDD33_IO
VDD33_IO
VDD33_V18
VDD33_VD11
XI
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
1.5 Pin Layout
Figure 1-2. TLK100 PIN DIAGRAM, TOP VIEW
Copyright © 2009, Texas Instruments Incorporated Introduction 3
Submit Documentation Feedback
Product Folder Link(s): TLK100
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
1 Introduction .............................................. 1 5.1 Transmit Path Encoder ............................. 26
5.2 Receive Path Decoder .............................. 28
1.1 Features .............................................. 1
5.3 10M Squelch ........................................ 30
1.2 Applications .......................................... 1
5.4 Auto MDI/MDI-X Crossover ........................ 31
1.3 General Description .................................. 1
5.5 Auto Negotiation .................................... 32
1.4 System Diagram ..................................... 1
6 Reset and Power Down Operation ................. 34
1.5 Pin Layout ............................................ 3
6.1 Hardware Reset .................................... 34
2 Pin Descriptions ......................................... 5
6.2 Software Reset ..................................... 34
2.1 Serial Management Interface ........................ 5
6.3 Power Down/Interrupt .............................. 34
2.2 MAC Data Interface .................................. 6
6.4 Power Down Modes ................................ 35
2.3 Clock Interface ....................................... 6
7 Design Guidelines ..................................... 36
2.4 LED Interface ........................................ 6
7.1 TPI Network Circuit ................................. 36
2.5 JTAG Interface ....................................... 7
7.2 Clock In (XI) Requirements ......................... 36
2.6 Reset and Power Down .............................. 7
7.3 Thermal Vias Recommendation .................... 38
2.7 Jumper Options ...................................... 8
8 Register Block ......................................... 39
8.1 Register Definition .................................. 43
2.8 10 Mb/s and 100 Mb/s PMD Interface ............... 9
8.2 Register Control Register (REGCR) ................ 52
2.9 Power and Bias Connections ........................ 9
8.3 Address or Data Register (ADDAR) ................ 52
2.10 Power Supply Configuration ........................ 10
8.4 Extended Registers ................................. 53
3 Configuration ........................................... 13
8.5 Cable Diagnostic Registers ......................... 60
3.1 Auto-Negotiation .................................... 13
9 Electrical Specifications ............................. 69
3.2 Auto-MDIX .......................................... 14
9.1 ABSOLUTE MAXIMUM RATINGS ................. 69
3.3 PHY Address ....................................... 15
9.2 THERMAL CHARACTERISTICS ................... 69
3.4 LED Interface ....................................... 16
9.3 RECOMMENDED OPERATING CONDITIONS .... 69
3.5 Loopback Functionality ............................. 17
9.4 DC CHARACTERISTICS ........................... 70
3.6 BIST ................................................ 18
9.5 POWER SUPPLY CHARACTERISTICS ........... 70
3.7 Cable Diagnostics .................................. 19
9.6 AC Specifications ................................... 71
4 Interfaces ................................................ 21
10 Appendix A: Digital Spectrum Analyzer (DSA)
4.1 Media Independent Interface (MII) ................. 21
Output .................................................... 83
4.2 Serial Management Interface ....................... 22
Revision History ............................................ 84
5 Architecture ............................................. 26
4 Contents Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLK100
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
2 Pin Descriptions
The TLK100 pins are classified into the following interface categories (each interface is described in the
sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Configuration (Jumper) Options
• 10/100 Mb/s PMD Interface
• Special Connect Pins
• Power and Ground pins
Note: Configuration pin option. See Section 2.7 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: OD Open Drain
Type: PD, PU Internal Pulldown/Pullup
Type: S Configuration Pin (All configuration pins have weak internal pullups or pulldowns. If
a different default value is needed, then use an external 2.2kΩ resistor. See
Section 2.7 for details.)
2.1 Serial Management Interface
PIN
TYPE DESCRIPTION
NAME NO.
MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The
MDC 32 I maximum MDC rate is 25 MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the
MII_TX_CLK or the MII_RX_CLK.
MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local
MDIO 33 I/O
controller or the TLK100 may drive the MDIO signal. This pin requires a pull-up resistor with value 1.5 kΩ.
Copyright © 2009, Texas Instruments Incorporated Pin Descriptions 5
Submit Documentation Feedback
Product Folder Link(s): TLK100
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