× ×
SDAS182 − APRIL 1990
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
D Independent Asychronous Inputs and
Outputs
D Bidirectional
D 32 Words by 9 Bits
D Programmable Depth
D Data Rates from 0 to 40 MHz
D Fall-Through Time . . . 22 ns Typ
D 3-State Outputs
description
This 576-bit memory uses advanced low-power
Schottky IMPACT-X technology and features
high speed and fast fall-through times. It consists
of two FIFOs organized as 32 words by 9 bits
each.
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. These FIFOs are
designed to process data at rates from 0 to 40
MHz in a bit-parallel format, word by word.
The SN74ALS2238 consists of bus-transceiver
circuits, two 32 × 9 FIFOs, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal FIFO
memories. Enables GAB and GBA are provided to
control the transceiver functions. The SAB and
SBA control pins are provided to select whether
real-time or stored data is transferred. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low level selects real-time data and a high
selects stored data. Eight fundamental
bus-management functions can be performed as
shown in Figure 1.
Data on the A or B data bus, or both, is written into
the FIFOs on a low-to-high transition at the load
clock (LDCKA or LDCKB) input and is read out on
a low-to-high transition at the unload clock
(UNCKA or UNCKB) input. The memory is full
when the number of words clocked in exceeds, by
the defined depth, the number of words clocked
out.
When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is
empty, UNCK signals have no effect.
Copyright 1990, Texas Instruments Incorporated
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IMPACT-X is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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RSTA
DAF
A0
A1
A2
GND
A3
A4
A5
A6
GND
V
CC
A7
A8
LDCKA
FULLA
UNCKB
EMPTYB
SAB
GAB
RSTB
DBF
B0
B1
B2
GND
B3
B4
B5
B6
GND
V
CC
B7
B8
LDCKB
FULLB
UNCKA
EMPTYA
SBA
GBA
(TOP VIEW)
B2
GND
V
CC
B3
B4
B5
B6
GND
V
CC
B7
B8
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38
37
36
35
34
33
32
31
30
29
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7
8
9
10
11
12
13
14
15
16
17
GND
V
CC
A3
A4
A5
A6
GND
V
CC
A7
A8
LDCKA
20 21 22 23
FN PACKAGE
(TOP VIEW)
DBF
GND
B0
B1
54 321644
A2
A1
A0
GND
DAF
RSTA
RSTB
EMPTYA
UNCKA
FULLB
LDCKB
FULLA
UNCKB
EMPTYB
SAB
GAB
GBA
SBA
42 41 4043
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