TI1-TMS29F010.pdf

preview
试读
36页
需积分: 0 0 下载量 152 浏览量 更新于2022-12-10 4 收藏 462KB PDF 举报
【TI TMS29F010概述】 TI的TMS29F010是一款131072位（1048576位）的5伏单电源可编程只读存储器（PROM），具备电擦除和重编程功能。这款设备采用8个独立的16K字节扇区组织，提供了70ns到120ns之间的不同访问时间选择。 【主要特性】 1. **单电源供电**：TMS29F010工作在5V电压范围±10%，适应性较强。 2. **存储结构**：器件由8个等大小的16K字节扇区构成，允许任意组合的扇区进行擦除和设置为只读。 3. **兼容性**：命令集与JEDEC 1M位EEPROM兼容，方便集成到已有系统中。 4. **自动操作**：内建的微处理器控制状态机执行擦除和字节编程操作，且擦除和扇区/芯片擦除功能完全自动化。 5. **耐用性**：该器件可承受100000次的编程/擦除周期，具有良好的耐久性。 6. **低功耗**：在读取模式下，电流典型值为20mA；在编程/擦除模式下，电流典型值为30mA，适合节能应用。 7. **兼容性**：所有输入/输出都与TTL兼容，易于系统集成。 【数据保护与操作】 TMS29F010通过硬件扇区保护功能实现任意扇区组合的数据保护。设备操作是通过将JEDEC标准命令写入命令寄存器来选择的，该寄存器作为内部状态机的输入，解读命令，控制擦除和编程操作，输出设备状态，读取存储数据，并输出设备算法选择代码。在上电初始化时，设备默认进入读取模式。 【封装与应用】 TMS29F010采用32引脚塑封芯片载体（FM后缀），引脚间距为1.27mm（50mil）。需要注意的是，德州仪器的半导体产品在可用性、标准保修以及在关键应用中的使用等方面有重要的声明和免责声明，这些信息通常会在产品文档的结尾部分给出。 TI的TMS29F010是一款高集成度、高性能的单电源PROM，适用于需要频繁编程和数据保护的多种应用场景，如嵌入式系统、数据存储和微控制器扩展等领域。其独特的扇区保护功能和JEDEC兼容性使得它成为开发人员的一个可靠选择。

  
 
SMJS840A − NOVEMBER 1997 − REVISED JUNE 1998
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
D Single Power Supply
5 V ± 10%
D Organization . . . 131072 by 8 Bits
D Eight Equal Sectors of 16K Bytes
− Any Combination of Sectors Can Be
Erased
− Any Combination of Sectors Can Be
Marked as Read-Only
D Compatible With JEDEC EEPROM
Command Set
D Fully Automated On-Chip Erase and
Byte-Program Operations
D 100000 Program/Erase Cycles
D Compatible With JEDEC Byte-Wide Pinouts
D Low-Current Consumption
− Active Read . . . 20 mA Typical
− Active Program/Erase . . . 30 mA Typical
D All Inputs/Outputs TTL-Compatible
description
The TMS29F010 is a 131072 by 8-bit
(1048576-bit), 5-V single-supply, programmable
read-only memory device that can be electrically
erased and reprogrammed. This device is
organized as eight independent 16K-byte sectors
and is offered with access times between 70 ns
and 120 ns.
An on-chip state machine controls the program and erase operations. The embedded byte-program and
sector/chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 1M-bit
EEPROMs. Data-protection of any sector combination is accomplished using a hardware sector-protection
feature.
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine that
interprets the commands, controls the erase and programming operations, outputs the status of the device,
outputs data stored in the device, and outputs the device algorithm-selection code. On initial power-up
operation, the device defaults to the read mode.
The TMS29F010 is offered in a 32-pin plastic leaded chip carrier (FM suffix) using 1.27-mm (50-mil) lead pitch.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NC
A[0:16] Address Inputs
DQ[0:7] Inputs (programming)/Outputs
E
Chip Enable
G
Output Enable
V
CC
5-V Power Supply
V
SS
Ground
W
Write Enable
NC No Connection
PIN NOMENCLATURE
3213231
14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
G
A10
E
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
430
15 16 17 18 19
DQ1
DQ2
DQ3
DQ4
DQ5
A12
A15
A16
W
NC
FM PACKAGE
(TOP VIEW)
20
DQ6
V
CC
V
SS
Copyright 1998, Texas Instruments Incorporated
  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-

  
 
SMJS840A − NOVEMBER 1997 − REVISED JUNE 1998
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device symbol nomenclature
Temperature Range Designator
L = Commercial (0°C to 70°C)
E = Extended (− 40°C to 85°C)
Q = Automotive (− 40°C to 125°C)
Package Designator
FM = Plastic Leaded Chip Carrier
Program/Erase Endurance
C5 = 100000 Cycles
Speed Designator
-70 = 70 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-10 C5 FM LTMS29F010

  
 
SMJS840A − NOVEMBER 1997 − REVISED JUNE 1998
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
block diagram
V
CC
Detector
Command Register
State Control
Timer
Erase-Voltage
Generator
Program-Voltage
Generator
Input/Output Buffers
Data Latch
Column Decoder
Row-Decoder
A
d
d
r
e
s
s
L
a
t
c
h
Column-Gating
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
16K × 8-Bit Array
Chip-Enable
Output-Enable
Logic
DQ0−DQ7
V
CC
V
SS
W
E
G
A0−A16

  
 
SMJS840A − NOVEMBER 1997 − REVISED JUNE 1998
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory sector architecture
1FFFFh
16K-Byte Sector 7
16K-Byte Sector 6
16K-Byte Sector 5
16K-Byte Sector 4
16K-Byte Sector 3
16K-Byte Sector 2
16K-Byte Sector 1
16K-Byte Sector 0
A16 A15 A14 Address Range
Sector 0 0 0 0 00000h − 03FFFh
Sector 1 0 0 1 04000h − 07FFFh
Sector 2 0 1 0 08000h − 0BFFFh
Sector 3 0 1 1 0C000h − 0FFFFh
Sector 4 1 0 0 10000h − 13FFFh
Sector 5 1 0 1 14000h − 17FFFh
Sector 6 1 1 0 18000h − 1BFFFh
Sector 7 1 1 1 1C000h − 1FFFFh
18000h
17FFFh
1C000h
1BFFFh
14000h
13FFFh
10000h
0FFFFh
0C000h
0BFFFh
08000h
07FFFh
04000h
03FFFh
00000h

  
 
SMJS840A − NOVEMBER 1997 − REVISED JUNE 1998
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
operation
Table 1 summarizes the operation modes.
Table 1. Operation Modes
MODE
FUNCTIONS
†
MODE
E G W A0
A1 A6
A9 DQ0−DQ7
Read V
IL
V
IL
V
IH
A0 A1 A6 A9 Data out
Output disable V
IL
V
IH
V
IH
X X X X Hi-Z
Standby and write inhibit V
IH
X X X X X X Hi-Z
Algorithm-selection mode
V
IL
V
IL
V
IH
V
IL
V
IL
X
V
ID
Manufacturer-equivalent code
01h
Algorithm-selection mode
V
IL
V
IL
V
IH
V
IH
V
IL
X
V
ID
Device-equivalent code 20h
Write
‡
V
IL
V
IH
V
IL
A0 A1 A6 A9 Data in
Sector-protect
§
V
IL
V
ID
V
IL
X X X V
ID
X
Sector-protect verify
§
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
V
ID
Data out
Sector-unprotect
§
(see Note 1)
V
ID
V
ID
V
IL
X X V
IL
V
ID
X
Sector-unprotect verify
§
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
ID
Data out
Erase operations V
IL
V
IH
See
Note 2
See
Note 2
See
Note 2
See
Note 2
See
Note 2
See Note 2
†
X can be V
IL
or V
IH
.
‡
See Table 3 for valid address and data during write (byte program).
§
Operation at V
CC
= 5.0 V and T
A
= 25°C.
NOTES: 1. Address pins A7, A12 = V
IH
.
2. See Figure 6 through Figure 9.
read mode
To read the output of the TMS29F010, a low-level logic signal is applied to the E
and G pins. When two or more
TMS29F010 devices are connected in parallel, the output of any one device can be read without interference.
The E
pin is power control and is used for device selection. The G pin is output control and is used to gate the
data output onto the bus from the selected device.
The address-access time (t
AVQV
) is the delay from stable address to valid output data. The chip-enable access
time (t
ELQV
) is the delay from E = V
IL
and stable addresses to valid output data. The output-enable access time
(t
GLQV
) is the delay from G = V
IL
to valid output data when E = V
IL
and addresses are stable for at least the
duration of t
AVQV
−t
GLQV
.
standby mode
The I
CC
supply current is reduced by applying a logic-high level on E to enter the standby mode. In the standby
mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on E
reduces the
current to 100 µA maximum. Applying a TTL logic-high level on E
reduces the current to 1 mA maximum.
If the TMS29F010 is deselected during erasure or programming, the device continues to draw active current
until the operation is complete.
output disable
When either G
= V
IH
or E = V
IH
, output from the device is disabled and the output pins (DQ0−DQ7) are placed
in the high-impedance state.

剩余35页未读，继续阅读

资源推荐
资源评论
不觉明了
  • 粉丝: 6213
  • 资源: 5760
上传资源 快速赚钱
voice
center-task 前往需求广场，查看用户热搜

最新资源