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TI1-TMS44400-60DJ.pdf
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TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization...1048576 × 4
D
Single 5-V Power Supply for TMS44400/P
(±10% Tolerance)
D
Single 3.3-V Power Supply for TMS46400/P
(±10% Tolerance)
D
Low Power Dissipation (TMS46400P only)
200-µA CMOS Standby
200-µA Self Refresh
300-µA Extended-Refresh Battery
Backup
D
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME TIME TIME OR WRITE
(t
RAC
)(t
CAC
)(t
AA
) CYCLE
(MAX) (MAX) (MAX) (MIN)
’4x400/P-60 60 ns 15 ns 30 ns 110 ns
’4x400/P-70 70 ns 18 ns 35 ns 130 ns
’4x400/P-80 80 ns 20 ns 40 ns 150 ns
D
Enhanced Page-Mode Operation for Faster
Memory Access
D
CAS-Before-RAS (CBR) Refresh
D
Long Refresh Period
1024-Cycle Refresh in 16 ms
128 ms (MAX) for Low-Power,
Self-Refresh Version (TMS4x400P)
D
3-State Unlatched Output
D
Texas Instruments EPIC CMOS Process
D
Operating Free-Air Temperature Range
0°C to 70°C
AVAILABLE OPTIONS
DEVICE
POWER
SUPPLY
SELF-REFRESH
BATTERY
BACKUP
REFRESH
CYCLES
TMS44400 5 V — 1024 in 16 ms
TMS44400P 5 V Yes 1024 in 128 ms
TMS46400 3.3 V — 1024 in 16 ms
TMS46400P 3.3 V Yes 1024 in 128 ms
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x400 and TMS4x400P are offered in a 20/26-lead plastic small-outline (TSOP) package (DGA suffix)
and a 300-mil 20/26-lead plastic surface-mount SOJ package (DJ suffix). Both packages are characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
PIN NOMENCLATURE
A0–A9 Address Inputs
CAS
Column-Address Strobe
DQ1– DQ4 Data In
OE
Output Enable
RAS
Row-Address Strobe
V
CC
5-V or 3.3-V Supply
V
SS
Ground
W
Write Enable
DJ PACKAGE
(TOP VIEW)
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
DGA PACKAGE
(TOP VIEW)
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION
description
The TMS4x400 series is a set of high-speed,
4194304-bit dynamic random-access memories
(DRAMs), organized as 1048576 words of four
bits each. The TMS4x400P series is a set of
high-speed, low-power, self-refresh with
extended-refresh, 4194304-bit DRAMs,
organized as 1048576 words of four bits each.
Both series employ state-of-the-art enhanced
performance implanted CMOS (EPIC
)
technology for high performance, reliability, and
low power.
Copyright 1996, Texas Instruments Incorporated
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol
†
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
CAS
W
OE
9
10
11
12
14
15
16
17
18
4
23
3
22
20D10/21D0
20D19/21D9
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
23C22
23,21D 24
,25 EN
G25
A
0
1048575
RAM 1024K × 4
&
A9
5
1
2
24
25
A,Z26
A,22D
26
DQ1
DQ2
DQ3
DQ4
†
This symbol is in accordance with ANSI/ IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DJ package.
functional block diagram
A0
A1
A9
16
Timing and Control
Column-
Address
Buffers
Row-
Address
Buffers
I/O
Buffers
1 of 16
Selection
Data-
In
Reg.
Data-
Out
Reg.
Column Decode
Sense Amplifiers
R
o
w
D
e
c
o
d
e
16
128K Array
128K Array
128K Array
128K Array
128K Array
128K Array
RAS
CAS W
DQ1–DQ4
4
4
OE
2
8
10
10
16
16
2
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operation
enhanced page mode
Enhanced-page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row-address setup and hold and address multiplex is
eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS
low
time and the CAS
page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by
column addresses A0 through A9 can be accessed without intervening RAS
cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS
. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS
transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS
. In this case, data is obtained after t
CAC
maximum (access time from CAS
low) if t
AA
maximum (access time from column address) has been satisfied. In the event that column addresses
for the next cycle are valid at the time CAS
goes high, access time for the next cycle is determined by the later
occurrence of t
CAC
(acces time from CAS low) or t
CPA
(access time from column precharge).
address (A0–A9)
Twenty address bits are required to decode any one of the 1048576 storage-cell locations. Ten row-address
bits are set up on inputs A0 through A9 and latched onto the chip by RAS
. The ten column-address bits are set
up on A0 through A9 and latched onto the chip by CAS
. All addresses must be stable on or before the falling
edges of RAS
and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS
is used as a chip select, activating the output buffer, as well as latching the address bits into
the column-address buffer.
write enable (W
)
The read or write mode is selected through W
input. A logic high on W selects the read mode and a logic low
selects the write mode. W
can be driven from standard TTL circuits (TMS44400/P) or low voltage TTL circuits
(TMS46400/P) without a pullup resistor. The data input is disabled when the read mode is selected. When W
goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting
a write operation independent of the state of OE
. This permits early-write operation to complete with OE
grounded.
data in/out (DQ1–DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS
and OE
are brought low. In a read cycle, the output becomes valid after all access times are satisfied. The output remains
valid while CAS
and OE are low. CAS or OE going high returns the output to a high-impedance state. This is
accomplished by bringing OE
high prior to applying data, satisfying the OE to data delay hold time (t
OED
).
output enable (OE
)
OE
controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE
low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS
and CAS to be brought low for the output buffers to go into the low-impedance
state. They remain in the low-impedance state until either OE
or CAS is brought high.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS
-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS
-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS
at V
IL
after a read operation and cycling RAS after a specified
precharge period, similar to a RAS
-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS
-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS
low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-µA (TMS46400P) or 500-µA
(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 µs while holding RAS
low for less than 1 µs. To minimize current consumption, all
input levels need to be at CMOS levels (V
IL
≤ 0.2 V, V
IH
≥ V
CC
– 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS
low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles must include at least one refresh
(RAS
-only or CBR) cycle.
test mode
The test mode is initiated with a CBR refresh cycle while simultaneously holding W
low (WCBR). The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device
exits test mode if a CBR refresh cycle with W
held high or a RAS-only refresh (ROR) cycle is performed.
The TMS4x400/P is configured as a 512K × 8 bit device in test mode, where each DQ pin has a separate 2-bit
parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin
separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to
reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the
others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for
this series.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
test mode (continued)
Test Mode Cycle
Entry Cycle
Exit Cycle
Normal
Mode
RAS
CAS
W
Figure 1. Test-Mode Cycle Timing
†
†
The states of W, data in, and address are defined by the type of cycle used during test mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
: TMS44400, TMS44400P – 1.0 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . .
TMS46400, TMS46400P – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . .
Voltage range on any pin (see Note 1) TMS44400, TMS44400P – 1.0 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . .
TMS46400, TMS46400P – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . .
Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
TMS44400/P TMS46400/P
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 3 3.3 3.6 V
V
IH
High-level input voltage 2.4 6.5 2 V
CC
+ 0.3 V
V
IL
Low-level input voltage (see Note 2) –1 0.8 – 0.3 0.8 V
T
A
Operating free-air temperature 0 70 0 70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
ADVANCE INFORMATION
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