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TI1-TIBPAL22V10-5C.pdf
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TI1-TIBPAL22V10-5C.pdf
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TIBPAL22V10-5C
HIGH-PERFORMANCE IMPACT-XL PROGRAMMABLE ARRAY LOGIC CIRCUIT
SRPS028A – MAY 1992 – REVISED OCTOBER 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
• High-Performance Operation:
f
max
(External Feedback) ...117 MHz
Propagation Delay ...5 ns Max
• Increased Logic Power – Up to 22 Inputs
and 10 Outputs
• Increased Product Terms – Average of 12
Per Output
• Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
• Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
• Power-Up Clear on Registered Outputs
• TTL-Level Preload for Improved Testability
• Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
• Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
• AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
• JEDEC Approved Revolutionary Power and
Ground Pinout for 28-Pin Chip Carrier
Reduces Cross Talk and Ground Bounce
• JEDEC File Compatibility Allows Previous
’22V10 Designs to be Programmed Into the
TIBPAL22V10-5C Without Modifications
description
The TIBPAL22V10-5C is a programmable array logic device featuring high speed and functional equivalency
when compared to presently available devices. The TIBPAL22V10-5C is implemented with the familiar
sum-of-products (AND-OR) logic structure featuring programmable output logic macrocells. These
IMPACT-XL circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-
tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
This device contains up to 22 inputs and 10 outputs. It incorporates the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs can be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
This device is covered by U.S. Patent 4,410,987.
IMPACT-XL is a trademark of Texas Instruments Incorporated.
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O/Q
GND
I/O/Q
V
CC
I/O/Q
GND
I/O/Q
I/O/Q
GND
I/O/Q
V
CC
I/O/Q
GND
I/O/Q
426
14 15 16 17 18
I
I
I
I
I
I
I/O/Q
I/O/Q
I
I
CLK/I
I
I
FN PACKAGE
(TOP VIEW)
I
TIBPAL22V10-5C
HIGH-PERFORMANCE IMPACT-XL PROGRAMMABLE ARRAY LOGIC CIRCUIT
SRPS028A – MAY 1992 – REVISED OCTOBER 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10-5C offers quick design and development of custom LSI functions with complexities of 500 to 800
equivalent gates. Since each of the ten output pins can be individually configured as inputs on either a temporary
or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs
are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will verify as open.
The TIBPAL22V10-5C is characterized for operation from 0°C to 75°C.
TIBPAL22V10-5C
HIGH-PERFORMANCE IMPACT-XL PROGRAMMABLE ARRAY LOGIC CIRCUIT
SRPS028A – MAY 1992 – REVISED OCTOBER 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
functional block diagram (positive logic)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
12
14
EN
16
16
14
12
10
22
22
1
10
&
44 x 132
I/O/Q
I/O/Q
I/O/Q
I/O/Q
EN
EN
EN
EN
EN
EN
EN
EN
EN
10
10
8
8
10
11
CLK/I
I
Set
Reset
1S
R
C1
denotes fused inputs
Output
Logic
Macrocell
TIBPAL22V10-5C
HIGH-PERFORMANCE IMPACT-XL PROGRAMMABLE ARRAY LOGIC CIRCUIT
SRPS028A – MAY 1992 – REVISED OCTOBER 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
0 4 8 1216202428
Increment
First Fuse Numbers
32 36 40
Macro-
cell
R = 5809
P = 5808
R = 5811
P = 5810
R = 5813
P = 5812
R = 5815
P = 5814
R = 5817
P = 5816
logic diagram (positive logic)
Asynchronous Reset
4
25
5
23
7
2
3
(to all registers)
0
440
880
1496
2112
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
396
924
1452
2156
2860
27
26
I
I
28
I
1
CLK/I
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