TI1-TM893NBM36H.pdf
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TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization
TM893NBM36H/I ...8388608 × 36
D
Single 5-V Power Supply (±10% Tolerance)
D
72-Pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
D
TM893NBM36H/I – Uses Sixteen 16M-Bit
and Eight 4M-Bit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
D
Long Refresh Period
32 ms (2048 Cycles)
D
All Inputs, Outputs, Clocks Fully
TTL-Compatible
D
3-State Output
D
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
D
Enhanced Page-Mode Operation With
CAS
-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
D
Present Detect
D
Operating Free-Air Temperature Range
0°C to 70°C
D
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME TIME TIME OR
t
RAC
t
AA
t
CAC
WRITE
CYCLE
(MAX) (MAX) (MAX) (MIN)
’893NBM36H/I-60 60 ns 30 ns 15 ns 110 ns
’893NBM36H/I-70 70 ns 35 ns 18 ns 130 ns
’893NBM36H/I-80 80 ns 40 ns 20 ns 150 ns
D
Gold-Tabbed Versions Available:
†
TM893NBM36H
D
Tin-Lead (Solder)-Tabbed Versions
Available:
TM893NBM36I
description
The TM893NBM36H/I is a 32M-byte dynamic random-access memory (DRAM) organized as four times
8388608 × 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen
TMS417400ADJ 4194304 × 4-bit DRAMs, each in a 24/26-lead plastic SOJ package, and eight TMS44100DJ
4194304 × 1-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling
capacitors. The TMS417400ADJ and TMS44100DJ are described in the TMS417400A (literature number
SMKS889) and TMS44100 (literature number SMHS561) data sheets, respectively. The TM893NBM36A
SIMM is available in the double-sided, BM leadless module for use with sockets.
operation
The TM893NBM36H/I operates as sixteen TMS417400ADJ DRAMs and eight TMS44100DJ DRAMs
connected as shown in the functional block diagram and in Table 1. The common I/O feature dictates the use
of early-write cycles to prevent contention on D and Q.
Table 1. Connection Table
DATA BLOCK
RASx
CASx
DATA
BLOCK
SIDE 1 SIDE 2
CAS
x
DQ0–DQ8 RAS0 RAS1 CAS0
DQ9–DQ17 RAS0 RAS1 CAS1
DQ18–DQ26 RAS2 RAS3 CAS2
DQ27–DQ35 RAS2 RAS3 CAS3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1997, Texas Instruments Incorporated
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