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TI1-TMS416800.pdf
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TI的TMS41x800系列是高性能的16777216位动态随机存取存储器(DRAMs),它们被组织为2097152个8位字。这些器件采用了德州仪器(TI)的尖端增强性能植入式互补金属氧化物半导体(EPIC)技术,旨在实现高速、高可靠性和低功耗。
TMS416800和TMS417800是该系列的成员,提供了三种不同的最大RAS访问时间:60ns、70ns和80ns,这使得它们在速度上有多种选择。所有的地址输入和数据输入线都通过片上锁存器进行锁存,简化了系统设计。数据输出则未被锁存,从而增加了系统的灵活性。
该系列DRAMs采用28引脚塑料表面贴装的小外形J型引脚(SOJ)封装,具有DZ后缀,其工作温度范围为0°C至70°C。值得注意的是,对于TMS417800,A11引脚内部没有连接(NC,无内部连接)。
在功能方面,TMS41x800系列支持增强的页模式操作,包括CAS-Before-RAS(CBR)刷新,这种特性允许更快的数据读取和写入。此外,器件还具有高阻态未锁定输出,这意味着在不需要时,输出可以被设置为高阻抗状态,减少对系统其他部分的影响。
引脚定义如下:
- A0到A11:地址输入,A11在TMS417800中为非连接。
- CAS:列地址选通,用于指定列地址。
- DQ0到DQ7:数据输入/输出引脚,用于传输数据。
- OE:输出使能,控制数据输出的开/关。
- RAS:行地址选通,用于指定行地址。
- VCC:5V电源电压。
- VSS:接地。
- W:写使能,控制数据写入。
封装形式为28引脚的DZ包,适用于表面安装,适合需要紧凑空间的电子设计。
TI在其数据表的末尾提到了关于产品可用性、标准保修以及在关键应用中使用其半导体产品的注意事项和免责声明,用户在使用前应仔细阅读并遵循这些条款。
TMS41x800系列是为高速、高密度存储需求设计的DRAM解决方案,适用于需要快速数据访问和可靠性的各种系统,如计算机、服务器、嵌入式系统和其他电子设备。其优化的EPIC技术确保了低功耗和高可靠性,而灵活的输出设计和多种访问时间选项则满足了不同应用的需求。
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization...2097152 × 8
D
Single 5 V Power Supply (±10% Tolerance)
D
Performance Ranges:
ACCESS ACCESS ACCESS READ OR
TIME TIME TIME WRITE
t
RAC
t
CAC
t
AA
CYCLE
MAX MAX MAX MIN
’41x800-60 60 ns 15 ns 30 ns 110 ns
’41x800-70 70 ns 18 ns 35 ns 130 ns
’41x800-80 80 ns 20 ns 40 ns 150 ns
D
Enhanced Page-Mode Operation With
CAS
-Before-RAS (CBR) Refresh
D
High-Impedance State Unlatched Output
D
High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
D
Operating Free-Air Temperature Range
0°C to 70°C
D
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC
) Technology by
Texas Instruments (TI)
description
The TMS41x800 series is a set of high-speed,
16777216-bit dynamic random-access memo-
ries (DRAMs) organized as 2097152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
These devices feature maximum RAS
access
times of 60 ns, 70 ns, and 80 ns. All addresses and
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The TMS416800 and TMS417800 are offered in
a 28-lead plastic surface-mount SOJ package
(DZ suffix). This package is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PIN NOMENCLATURE
A0–A11
†
Address Inputs
CAS
Column-Address Strobe
DQ0–DQ7 Data In/Data Out
OE
Output Enable
RAS
Row-Address Strobe
V
CC
5 V
V
SS
Ground
W
Write Enable
†
A11 is NC (no internal connection) for TMS417800.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
A11
†
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
DZ PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
EPIC and TI are trademarks of Texas Instruments Incorporated.
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by t
RASP
, the maximum row-address strobe
(RAS
) low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS
. The buffers act as transparent or flow-through latches while column-address strobe (CAS)
is high. The falling edge of CAS
latches the column addresses and enables the output. This feature allows the
devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins
as soon as the column address is valid rather than when CAS
goes low. This performance improvement is
referred to as enhanced page mode. A valid column address can be presented immediately after row-address
hold time has been satisfied, usually well in advance of the falling edge of CAS
. In this case, data is obtained
after t
CAC
max (access time from CAS low) if t
AA
max (access time from column address) and t
RAC
(access time
from RAS
) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes
high, access time for the next cycle is determined by the later occurrence of t
CPA
(access time from CAS
precharge) or t
CAC
.
address: A0–A11 (TMS416800) and A0–A10 (TMS417800)
Twenty-one address bits are required to decode one of 2097152 storage cell locations. For the TMS416800,
12 row-address bits are set up on A0 through A11 and latched on the chip by the RAS
. Nine column-address
bits are set up on A0 through A8. For the TMS417800, 11 row-address bits are set up on inputs A0 through A10
and latched on the chip by RAS
. Ten column-address bits are set up on A0 through A9. All addresses must be
stable on or before the falling edges of RAS
and CAS. RAS is similar to a chip enable because it activates the
sense amplifiers as well as the row decoder. CAS
is used as a chip select, activating the output buffers and
latching the address bits into the column-address buffers.
write enable (W
)
The read or write mode is selected through W
. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W
goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE
grounded.
data in (DQ0–DQ7)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS
with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS
is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE
must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ0–DQ7)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS
and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t
CAC
(which begins with
the negative transition of CAS
) as long as t
RAC
and t
AA
are satisfied.
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RAS-only refresh
TMS416800
A refresh operation must be performed at least once every 64 ms to retain data. The refresh operation can be
achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS
-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS
-only refresh.
TMS417800
A refresh operation must be performed at least once every 32 ms to retain data. The refresh operation can be
achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS
-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS
-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. The hidden refresh operation
is accomplished by holding CAS
at V
IL
after a read or write operation and cycling RAS after a specified
precharge period, similar to a RAS
-only refresh cycle. The external address is ignored, and the refresh address
is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is performed by bringing CAS
low earlier than RAS (see parameter t
CSR
) and then holding it low
after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling
RAS
. The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V
CC
level. The eight initialization cycles must include at least one refresh
(RAS
-only or CBR) cycle.
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol for TMS416800
†
A0
A1
A2
A3
A4
A5
A6
A7
10
11
12
13
16
17
18
19
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
RAS
CAS
W
OE
3
4
5
24
25
26
27
7
23
6
2
22
RAM 2M x 8
20D9/21D0
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
23,21D
24
,25EN
A,Z26
A8
20
A9
21
G25
A,22D
∇ 26
A
0
2 097 151
20D19
A10
9
20D18
A11
8
20D20
20D17/21D8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
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