TI1-TMS465169.pdf

low cost.

(DQ0−DQ15), with LCAS

going low enables its corresponding DQx pins.

Extended data out (EDO) allows for data output rates of up to 50 MHz for 50-ns devices. When keeping the same

row address while selecting random column addresses, the time for row-address setup and hold and address

multiplex is eliminated. The maximum number of columns that can be accessed is determined by t

maximum RAS

sense amplifiers as well as the row decoder. xCAS

The read or write mode is selected through W

the write mode. The data input is disabled when the read mode is selected. When W

(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation

low in an EDO read cycle, the DQ pins go into the high-impedance state as long as xCAS

In a delayed-write or read-modify-write cycle, xCAS

hold times referenced to this signal. In this cycle, OE