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TMS416160, TMS416160P, TMS418160, TMS418160P

TMS426160, TMS426160P, TMS428160, TMS428160P

1048576-WORD BY 16-BIT HIGH-SPEED DRAMS

SMKS160C – MAY 1995–REVISED NOVEMBER 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Organization...1048576 × 16

Single Power Supply (5 V or 3.3 V)

Performance Ranges:

ACCESS ACCESS ACCESS READ OR

TIME TIME TIME WRITE

RAC

CAC

CYCLE

MAX MAX MAX MIN

’4xx160/P-60 60 ns 15 ns 30 ns 110 ns

’4xx160/P-70 70 ns 18 ns 35 ns 130 ns

’4xx160/P-80 80 ns 20 ns 40 ns 150 ns

Enhanced Page-Mode Operation With

CAS

-Before-RAS (CBR) Refresh

Long Refresh Period and Self-Refresh

Option (TMS4xx160P)

3-State Unlatched Output

Low Power Dissipation

High-Reliability Plastic 42-Lead (DZ Suffix)

400-Mil-Wide Surface-Mount (SOJ) Package

and 44/50-Lead (DGE Suffix) Surface-Mount

Thin Small-Outline Package (TSOP)

Operating Free-Air Temperature Range

0°C to 70°C

Fabricated Using the Texas Instruments

Enhanced Performance Implanted CMOS

(EPIC) Technology

AVAILABLE OPTIONS

DEVICE

POWER

SUPPLY

SELF

REFRESH,

BATTERY

BACKUP

REFRESH

CYCLES

TMS416160

TMS416160P

TMS418160

TMS418160P

TMS426160

TMS426160P

TMS428160

TMS428160P

5 V

3.3 V

—

Yes

—

Yes

—

Yes

—

Yes

4096 in 64 ms

4096 in 128 ms

1024 in 16 ms

1024 in 128 ms

4096 in 64 ms

4096 in 128 ms

1024 in 16 ms

1024 in 128 ms

description

The TMS4xx160 series is a set of high-speed,

16777216-bit dynamic random-access memo-

ries (DRAMs) organized as 1048576 words of 16

bits each. The TMS4xx160P series is a similar

set of high-speed, low-power, self-refresh,

16777216-bit DRAMs organized as 1048576 words of 16 bits each. Both sets employ state-of-the-art

enhanced performance implanted CMOS (EPIC) technology for high performance, reliability, and low power

at low cost.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PIN NOMENCLATURE

A0– A11 Address Inputs

DQ0–DQ15 Data In/Data Out

LCAS

Lower Column-Address Strobe

UCAS

Upper Column-Address Strobe

NC No Internal Connection

Output Enable

RAS

Row-Address Strobe

5-V or 3.3-V Supply

‡

Ground

Write Enable

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LCAS

UCAS

DGE PACKAGE

(TOP VIEW)

RAS

A11

†

A10

†

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

RAS

A11

†

A10

†

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

LCAS

UCAS

DZ PACKAGE

(TOP VIEW)

‡

See Available Options Table.

†

A10 and A11 are NC for TMS4x8160 and TMS4x8160P.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TMS416160, TMS416160P, TMS418160, TMS418160P

TMS426160, TMS426160P, TMS428160, TMS428160P

1048576-WORD BY 16-BIT HIGH-SPEED DRAMS

SMKS160C – MAY 1995– REVISED NOVEMBER 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation

dual CAS

Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins

(DQ0–DQ15), with LCAS

corresponding to DQ0–DQ7 and UCAS corresponding to DQ8–DQ15. For read or

write cycles, the column address is latched on the first xCAS

falling edge. Each xCAS going low enables its

corresponding DQx pin with data associated with the column address latched on the first falling xCAS

edge.

All address setup and hold parameters are referenced to the first falling xCAS

edge.The delay time from xCAS

low to valid data out (see parameter t

CAC

) is measured from each individual xCAS to its corresponding DQx pin.

In order to latch in a new column address, both xCAS

pins must be brought high. The column-precharge time

(see parameter t

) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.

Keeping a column address valid while toggling xCAS

requires a minimum setup time, t

CLCH

. During t

CLCH

, at

least one xCAS

must be brought low before the other xCAS is taken high.

For early-write cycles, the data is latched on the first xCAS

falling edge. Only the DQs that have the

corresponding xCAS

low are written into. Each xCAS must meet t

CAS

minimum in order to ensure writing

into the storage cell. To latch a new address and new data, all xCAS

pins must be high and meet t

enhanced page mode

Page-mode operation allows faster memory access by keeping the same row address while selecting random

column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum

number of columns that can be accessed is determined by the maximum RAS

low time and the xCAS

page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without

intervening RAS

cycles.

Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling

edge of RAS

. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the

first xCAS

latches the column addresses. This feature allows the devices to operate at a higher data bandwidth

than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather

than when xCAS

transitions low. This performance improvement is referred to as enhanced page mode. A valid

column address may be presented immediately after t

RAH

(row-address hold time) has been satisfied, usually

well in advance of the falling edge of xCAS

. In this case, data is obtained after t

CAC

maximum (access time from

xCAS

low) if t

maximum (access time from column address) has been satisfied. In the event that column

addresses for the next page cycle are valid at the time xCAS

goes high, minimum access time for the next cycle

is determined by t

CPA

(access time from rising edge of the last xCAS).

address: A0–A11 (TMS4x6160, TMS4x6160P) and A0–A9 (TMS4x8160, TMS4x8160P)

Twenty address bits are required to decode 1 of 1048576 storage cell locations. For the TMS4x6160 and

TMS4x6160P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS

. Eight

column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS

. For the

TMS4x8160 and TMS4x8160P, 10 row-address bits are set up on A0–A9 and latched onto the chip by RAS

Ten column-address bits are set up on A0–A9 and latched onto the chip by the first xCAS

. All addresses must

be stable on or before the falling edge of RAS

and xCAS. RAS is similar to a chip enable in that it activates the

sense amplifiers as well as the row decoder. xCAS

is used as a chip select, activating its corresponding output

buffer and latching the address bits into the column-address buffers.

write enable (W

)

The read or write mode is selected through W

. A logic high on W selects the read mode and a logic low selects

the write mode. The data inputs are disabled when the read mode is selected. When W

goes low prior to xCAS

(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with

grounded.

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