TI-TMS626162-15DGE.pdf

Organization... 512K × 16 × 2 Banks

3.3-V Power Supply (±10% Tolerance)

Two Banks for On-Chip Interleaving

(Gapless Accesses)

High Bandwidth – Up to 83-MHz Data Rates

CAS Latency (CL) Programmable to 2 or 3

Cycles From Column-Address Entry

Burst Sequence Programmable to Serial or

Interleave

Auto-Refresh and Self-Refresh Capability

4K Refresh (Total for Both Banks)

High-Speed, Low-Noise, Low-Voltage TTL

Power-Down Mode

Compatible With JEDEC Standards

Operating, 0°C to 70°C

Storage, – 55°C to 150°C

OUTPUT

REFRESH

INTERVAL

(CL = 2)

REF

’626162-12A

12 ns 15 ns 9 ns 9 ns 64 ms

CL = CAS latency

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

CAS

Column-Address Strobe

CKE Clock Enable

RAS

Deactivate all banks X L L H L X H X DCAB

Bank activate/row-address entry SB = deac L L H H BS V V ACTV

Column-address entry/write operation SB = actv L H L L BS L V WRT

Column-address entry/write operation

SB = actv L H L L BS H V WRT-P

SB = actv L H L H BS H V READ-P

For execution of these commands on cycle n:

– CKE (n–1) must be high, or

must be satisfied for power-down exit, or

CES

SB = Bank selected by A11 at cycle n

¶

¶

CLK suspend exit on cycle (n + 1)

¶

¶

L H X X X X —

A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle

If setup time from CKE high to the next CLK high satisfies t

—

X N/A Hi-Z —

T = read

L N/A V ENBL

For execution of these commands on cycle n:

must be satisfied for power-down exit, or

CES

A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle

M = Masked input data