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TMS28F512A

65536 BY 8-BIT

FLASH MEMORY

SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

Organization . . . 65536 by 8 Bits

D

All Inputs/Outputs TTL-Compatible

D

V

CC

Tolerance ±10%

D

Maximum Access / Minimum Cycle Time

’28F512A-10 100 ns

’28F512A-12 120 ns

’28F512A-15 150 ns

’28F512A-17 170 ns

D

Industry-Standard Programming Algorithm

D

10000 and 1000 Program/Erase Cycles

D

Latchup Immunity of 250 mA on all Input

and Output Lines

D

Low Power Dissipation (V

CC

= 5.5 V)

– Active Write . . . 55 mW

– Active Read...165 mW

– Electrical Erase...82.5 mW

– Standby...0.55 mW

(CMOS-Input Levels)

D

Automotive Temperature Range

– 40°C to 125°C

description

The TMS28F512A Flash memory is a 65536 by

8-bit (524 288-bit), programmable read-only

memory that can be electrically bulk-erased and

reprogrammed. It is available in 10000 and 1000

program/erase endurance cycle versions.

The TMS28F512A is offered in a 32-lead plastic

leaded chip-carrier package with 1,25-mm

(50-mil) lead spacing (FM suffix).

The TMS28F512A is characterized for operation

in temperature ranges of 0°C to 70°C (FML suffix),

–40°C to 85°C (FME suffix), and –40°C to 125°C

(FMQ suffix).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PIN NOMENCLATURE

A0–A15 Address Inputs

DQ0– DQ7 Inputs (programming)/ Outputs

E Chip Enable

G

Output Enable

NC No Internal Connection

V

CC

5-V Power Supply

V

PP

12-V Power Supply

V

SS

Ground

W

Write Enable

FM PACKAGE

(TOP VIEW)

3213231

14

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

A14

A13

A8

A9

A11

G

A10

E

DQ7

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

430

15 16 17 18 19

DQ1

DQ2

DQ3

DQ4

DQ5

A12

A15

NC

V

W

NC

20

DQ6

PP

V

CC

V

SS

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TMS28F512A

65536 BY 8-BIT

FLASH MEMORY

SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation

Modes of operation are defined in Table 1.

Table 1. Operation Modes

FUNCTION

†

MODE

V

PP

‡

(1)

E

(22)

G

(24)

A0

(12)

A9

(26)

W

(31)

DQ0–DQ7

(13–15, 17–21)

Read V

PPL

V

IL

V

IL

X X

V

IH

Data Out

Output Disable V

PPL

V

IL

V

IH

X X

V

IH

Hi-Z

Read

Standby and Write Inhibit V

PPL

V

IH

X X X

X

Hi-Z

Algorithm Selection Mode

V

PPL

V

IL

V

IL

V

IL

V

ID

V

IH

Mfr Equivalent Code 89h

Algorithm

-

Selection

Mode

V

PPL

V

IL

V

IL

V

IH

V

ID

V

IH

Device Equivalent Code B8h

Read V

PPH

V

IL

V

IL

X X

V

IH

Data Out

Read /

Output Disable V

PPH

V

IL

V

IH

X X

V

IH

Hi-Z

Write

Standby and Write Inhibit V

PPH

V

IH

X X X

X

Hi-Z

Write V

PPH

V

IL

V

IH

X X

V

IL

Data In

†

X can be V

IL

or V

IH

.

‡

V

PPL

≤ V

CC

+ 2 V; V

PPH

is the programming voltage specified for the device. For more details, see recommended operating conditions.

read/output disable

When the outputs of two or more TMS28F512As are connected in parallel on the same bus, the output of any

particular device in the circuit can be read with no interference from the competing outputs of other devices. To

read the output of the TMS28F512A, a low-level signal is applied to the E

and G pins. All other devices in the

circuit should have their outputs disabled by applying a high-level signal to one of these pins.

standby and write inhibit

Active I

CC

current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA by applying

a high CMOS level on E

. In this mode, all outputs are in the high-impedance state. The TMS28F512A draws

active current when it is deselected during programming, erasure, or program/erase verification. It continues

to draw active current until the operation is terminated.

algorithm-selection mode

The algorithm-selection mode provides access to a binary code that identifies the correct programming and

erase algorithms. This mode is activated when A9 is forced to V

ID

. Two identifier bytes are accessed by toggling

A0. All other addresses must be held low.

A0 low selects the manufacturer equivalent code 89h, and A0 high

selects the device equivalent code B8h, as shown in Table 2.

Table 2. Algorithm-Selection Modes

IDENTIFIER

§

PINS

IDENTIFIER

§

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

Manufacturer Equivalent Code V

IL

1 0 0 0 1 0 0 1 89

Device Equivalent Code V

IH

1 0 1 1 1 0 0 0 B8

§

E = G = V

IL

, A1 – A8 = V

IL

, A9 = V

ID

, A10– A15 = V

IL

, V

PP

= V

PPL

.

programming and erasure

In the erased state, all bits are at a logic one. Before erasing the device, all memory bits must be programmed

to a logic zero. Afterwards, the entire chip is erased. At this point, the bits, now logic ones, can be programmed

accordingly. Refer to the fastwrite- and fasterase-algorithms for further detail.

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