【免费】TI-TMS416400.pdf资源-CSDN文库

需积分: 0 92 浏览量 2022-12-10 23:06:43 上传评论 4 收藏 443KB PDF 举报

资源详情

资源评论

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Electrical characteristics for TMS416400/P and

TMS417400/P is Production Data. Electrical

characteristics for TMS426400/P and

TMS427400/P is Product Preview only.

Organization...4194304 × 4

Single 5 V Power Supply for TMS41x400/P

(±10% Tolerance)

Single 3.3 V Power Supply for

TMS42x400/P (±0.3 V Tolerance)

Performance Ranges:

ACCESS ACCESS ACCESS READ OR

TIME TIME TIME WRITE

RAC

CAC

CYCLE

MAX MAX MAX MIN

’4xx400/P-60 60 ns 15 ns 30 ns 110 ns

’4xx400/P-70 70 ns 18 ns 35 ns 130 ns

’4xx400/P-80 80 ns 20 ns 40 ns 150 ns

Enhanced Page-Mode Operation With

CAS

-Before-RAS (CBR) Refresh

Long Refresh Period and Self-Refresh

Option (TMS4xx400P)

3-State Unlatched Output

Low Power Dissipation

High-Reliability Plastic 24/26-Lead

300-Mil-Wide Surface-Mount Small-Outline

J-Lead (SOJ) Package and 24/26-Lead

Surface-Mount Thin Small-Outline Package

(TSOP)

Operating Free-Air Temperature Range:

0°C to 70°C

EPIC (Enhanced Performance Implanted

CMOS) Technology

AVAILABLE OPTIONS

DEVICE

POWER

SUPPLY

SELF

REFRESH

BATTERY

BACKUP

REFRESH

CYCLES

TMS416400

TMS416400P

TMS417400

TMS417400P

TMS426400

TMS426400P

TMS427400

TMS427400P

5 V

3.3 V

—

Yes

—

Yes

—

Yes

—

Yes

4096 in 64 ms

4096 in 128 ms

2048 in 32 ms

2048 in 128 ms

4096 in 64 ms

4096 in 128 ms

2048 in 32 ms

2048 in 128 ms

These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines

are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

‡

See Available Options Table

PIN NOMENCLATURE

A0– A11

†

Address Inputs

CAS

Column-Address Strobe

DQ1–DQ4 Data In/Data Out

Output Enable

NC No Internal Connection

RAS

Row-Address Strobe

5-V or 3.3-V Supply

‡

Ground

Write Enable

DJ PACKAGE

(TOP VIEW)

DQ1

DQ2

RAS

DQ4

DQ3

CAS

A11

†

216

A10 A8

198

DGA PACKAGE

(TOP VIEW)

DQ1

DQ2

RAS

DQ4

DQ3

CAS

A11

†

216

A10 A8

198

†

A11 is NC for TMS4x7400/P.

description

The TMS4xx400 is a set of high-speed,

16777216-bit dynamic random-access memories

organized as 4194304 words of 4 bits each. The

TMS4xx400P series are high-speed, low-power,

self-refresh, 16777216-bit dynamic random-

access memories organized as 4194304 words of

4 bits each. The TMS4xx400 and TMS4xx400P

employ state-of-the-art EPIC

(Enhanced

Performance Implanted CMOS) technology for

high performance, reliability, and low power.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

EPIC is a trademark of Texas Instruments Incorporated.

TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS4xx400 and TMS4xx400P are each offered in a 24/26-lead plastic surface-mount TSOP (DGA suffix)

package and a 24/26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized

for operation from 0°C to 70°C.

operation

enhanced page mode

Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting

random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The

maximum number of columns that can be accessed is determined by t

RASP

, the maximum RAS low time.

Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the

falling edge of RAS

. The buffers act as transparent or flow-through latches while CAS is high. The falling edge

of CAS

latches the column addresses and enables the output. This feature allows the devices to operate at a

higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column

address is valid rather than when CAS

transitions low. This performance improvement is referred to as

enhanced page mode. A valid column address can be presented immediately after row-address hold time has

been satisfied, usually well in advance of the falling edge of CAS

. In this case, data is obtained after t

CAC

max

(access time from CAS

low) if t

max (access time from column address) and t

RAC

have been satisfied. In the

event that column address for the next cycle is valid at the time CAS

goes high, access time for the next cycle

is determined by the later occurrence of t

CPA

or t

CAC

address: A0–A11 (TMS4x6400/P) and A0–A10 (TMS4x7400/P)

Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. For the TMS4x6400 and

TMS4x6400P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address

strobe (RAS

). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11

row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS

. Eleven column-address

bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS

and CAS.

RAS

is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used

as a chip select, activating the output buffers and latching the address bits into the column-address buffers.

write enable (W)

The read or write mode is selected through W

. A logic high on W selects the read mode, and a logic low selects

the write mode. The data inputs are disabled when the read mode is selected. When W

goes low prior to CAS

(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with

grounded.

data in (DQ1–DQ4)

Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge

of CAS

or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and

the data is strobed in by CAS

with setup and hold times referenced to this signal. In a delayed-write or

read-modify-write cycle, CAS

is already low, and the data is strobed in by W with setup and hold time referenced

to this signal. In a delayed-write or read-modify-write cycle, OE

must be high to bring the output buffers to the

high-impedance state prior to impressing data on the I/O lines.

data out (DQ1–DQ4)

Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS

and OE

are brought low. In a read cycle, the output becomes valid after the access time interval t

CAC

(which begins with

the negative transition of CAS

) as long as t

RAC

and t

are satisfied.

TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

RAS-only refresh

TMS4x6400, TMS4x6400P

A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This

can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits

in each row that is selected. A RAS

-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffers remain in the high-impedance state. Externally generated addresses

must be used for a RAS

-only refresh.

TMS4x7400, TMS4x7400P

A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This

can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits

in each row that is selected. A RAS

-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffers remain in the high-impedance state. Externally generated addresses

must be used for a RAS

-only refresh.

hidden refresh

Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding

CAS

at V

after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only

refresh cycle. The external address is ignored, and the refresh address is generated internally.

CAS

-before-RAS (CBR) refresh

CBR refresh is utilized by bringing CAS

low earlier than RAS (see parameter t

CSR

) and holding it low after RAS

falls (see parameter t

CHR

). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The

external address is ignored, and the refresh address is generated internally.

battery-backup refresh

TMS4x6400P

A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current

is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25 µs while

holding RAS

low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels

< 0.2 V, V

> V

– 0.2 V).

TMS4x7400P

A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current

is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5 µs while

holding RAS

low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels

< 0.2 V, V

> V

– 0.2 V).

self refresh (TMS4xx400P)

The self-refresh mode is entered by dropping CAS

low prior to RAS going low. Then CAS and RAS are both

held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external

address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,

both RAS

and CAS are brought high to satisfy t

CHS

. Upon exiting self-refresh mode, a burst refresh (refresh a

full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures

the DRAM is fully refreshed.

power up

To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles

is required after power up to the full V

level. These eight initialization cycles must include at least one refresh

(RAS

-only or CBR) cycle.

剩余29页未读，继续阅读

评论收藏

内容反馈

TI-TMS416400.pdf

评论0

最新资源

TI-TMS416400.pdf

评论0

最新资源

相关推荐

TI-TMS416400A.pdf

TI-TMS37145.pdf

TI-TMS37157.pdf

TI-TMS2516.pdf

TI-TMS416809.pdf

TI-TMS55160.pdf

TI-TMS4416.pdf

TI-TMS44409.pdf

TI-TMS45160.pdf

TI-TMS626812.pdf

TI-TMS416160.pdf

TI-TMS44100.pdf

TI-TMS44400-70DJ.pdf

TI-TMS55165-60DGH.pdf

TI-TMS626162-15DGE.pdf

TI-TMS44400-60DGA.pdf

TI-TMS4C2972-26DT.pdf

TI-TMS418160A-60DZ.pdf

TI-TMS29F800B-100BDBJQ.pdf

1_sixyin-music-source-v1.0.7.js

植物大战僵尸杂交版v2.0安装程序.exe

洛雪音乐助手自定义音源v1.2.0下载.zip

植物大战僵尸杂交版v2.0.zip

植物大战僵尸杂交版v2.0.88安装程序.zip

misaka-v3.3.8.zip

TiggerRamDiskV4.2Beta1-Win.zip

大麦抢票_BP全自动抢购教程+注意事项.rar

Flyme10图标包_1.0.0_1.apk

C语言程序设计第四版何钦铭课后习题及答案.pdf