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’44409/P-60 60 ns 15 ns 30 ns 25 ns

’44409/P-70 70 ns 18 ns 35 ns 30 ns

’44409/P-80 80 ns 20 ns 40 ns 35 ns

Extended Data Out (EDO) Operation

CAS-Before-RAS (CBR) Refresh

3-State Unlatched Output

Low Power Dissipation

All Inputs/Outputs and Clocks are

TTL-Compatible

Long Refresh Period

– 1 024 Cycle Refresh in 16 ns (max)

– 128 ms on Low Power, Self-Refresh

Version (TMS44409P Only)

Operating Free-Air Temperature Range

0°C to 70°C

description

The TMS44409 is a high-speed 4194304-bit

dynamic random-access memory (DRAM) orga-

nized as 1048576 words of four bits each. This

device features maximum RAS

access times of

60 ns, 70 ns and 80 ns. Maximum power

consumption is as low as 385 mW operating and

6 mW standby. All inputs and outputs, including

clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system

design. Data out is unlatched to allow greater system flexibility.

The TMS44409P is a high-speed, low-power, self-refresh version of the TMS44409 DRAM.

All versions of the TMS44409/P are offered in a 300-mil 20/26 J-lead plastic surface-mount SOJ package (DJ

suffix) and a 20/26-lead plastic small outline package (DGA suffix). These devices are characterized for

operation from 0°C to 70°C.

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

ADVANCE INFORMATION

DQ4

DQ3

CAS

DQ1

DQ2

RAS

DQ4

DQ3

CAS

DQ1

DQ2

RAS

PIN NOMENCLATURE

A0–A9 Address Inputs

CAS

Column-Address Strobe

DQ1 – DQ4 Data In/ Data Out

Output Enable

RAS

Row-Address Strobe

5-V Supply

Ground

Write Enable

DJ PACKAGE

(TOP VIEW)

DGA PACKAGE

(TOP VIEW)

TMS44409, TMS44409P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMHS563 – JULY1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Timing and Control

Column-

Address

Buffers

Row-

Address

Buffers

I/O

Buffers

4 of 16

Selection

Column Decode

Sense Amplifiers

128K Array

DQ1–DQ4

RAS

CAS W OE

Data-

Reg.

Data-

Out

Reg.

operation

extended data out

Extended data out allows for data output rates of up to 40 MHz for 60-ns devices. When keeping the same row

address while selecting random column addresses, the time for row-address setup and hold and address

multiplex is eliminated. The maximum number of columns that can be accessed is determined by t

RASP

, the

maximum RAS

low time.

Extended data out does not place the DQs into the high-impedance state with the rising edge of CAS

. The output

remains valid for the system to latch the data. After CAS

goes high, the DRAM decodes the next address. OE

and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation

benefit.

address (A0–A9)

Twenty address bits are required to decode one of 1048576 storage cell locations. Ten row-address bits are

set up on A0 through A9 and latched onto the chip by the row-address strobe (RAS

). The ten column-address

bits are set up on pins A0 through A9 and latched onto the chip by the column-address strobe (CAS

). All

addresses must be stable on or before the falling edges of RAS

and CAS. RAS is similar to a chip-enable in

that it activates the sense amplifiers as well as the row decoder.

output enable (OE

)

controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought

low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two

methods for placing the DQs into the high-impedance state and keeping them that way during CAS

high time.

The first method is to transition OE

high before CAS transitions high and keep OE high for t

CHO

past the CAS

transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second

method is to have OE

low as CAS transitions high. Then OE can pulse high for a minimum of t

OEP

anytime during

CAS

high time, thus, disabling the DQs regardless of further transitions on OE until CAS falls again (see

Figure 7).

ADVANCE INFORMATION

TMS44409, TMS44409P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMHS563 – JULY1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

write enable (W)

The read or write mode is selected through the write-enable (W

) input. A logic high on the W input selects the

read mode and a logic low selects the write mode. The data input is disabled when the read mode is selected.

When W

goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle,

permitting a write operation independent of the state of OE

. This permits early-write operation to be completed

with OE

grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is

high (see Figure 8).

data in/data out (DQ1–DQ4)

Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, data is strobed

in by the later falling edge of CAS

or W with setup and hold times referenced to the latter edge. The DQs drive

valid data after all access times are met and remain valid except in the cases described in the W

and OE

descriptions (above).

refresh

A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing

each of the 1 024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A

RAS

-only operation can be used by holding CAS at the high (inactive) level, thus conserving power as the output

buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS

-only

refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished

by holding CAS

at V

after a read operation and cycling RAS after a specified precharge period, similar to a

RAS

-only refresh cycle. The external address is ignored during the hidden-refresh cycle.

CAS

-before-RAS (CBR) refresh

CBR refresh is utilized by bringing CAS

low earlier than RAS (see parameter t

CSR

) and holding it low after RAS

falls (see parameter t

CHR

). For successive CBR-refresh cycles, CAS can remain low while cycling RAS. The

external address is ignored and the refresh address is generated internally.

self-refresh (TMS44409P)

The self-refresh mode is entered by dropping CAS

low prior to RAS going low. CAS and RAS are both held low

for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required

because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS

and CAS

are brought high to satisfy t

CHS

. Upon exiting the self-refresh mode, a burst refresh (refresh of a full set of row

addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully

refreshed.

power up

To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles

is required after power up to the full V

level is achieved. These eight initialization cycles need to include at

least one refresh (RAS

only or CBR) cycle.

test mode

A design for test (DFT) mode is incorporated in the TMS44409. A CBR with W

low (WCBR) cycle is used to enter

the test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data

is written into the array through DQ1. Data is compared upon reading and if all bits are equal, all DQ pins go

high. If any one bit is different, a DQ pin goes low. Any combination of read, write, read-write, or page-mode

can be used in the test mode. The test-mode function reduces test times by enabling the 1-megabit × 4 DRAM

to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS

-only or CBR-refresh cycle

is used to exit the DFT mode.

ADVANCE INFORMATION

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