没有合适的资源？快使用搜索试试~ 我知道了~
TI-TVP5146M2.pdf
需积分: 10 0 下载量 168 浏览量
2022-12-04
00:03:11
上传
评论 4
收藏 912KB PDF 举报
温馨提示
试读
108页
TI-TVP5146M2.pdf
资源推荐
资源详情
资源评论
TVP5146M2
NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder
With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb
Filter, and SCART Support
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES141H
July 2005–Revised February 2012
TVP5146M2
www.ti.com
SLES141H –JULY 2005– REVISED FEBRUARY 2012
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features ...................................................................................................................... 9
1.2 Description ................................................................................................................. 10
1.3 Applications ................................................................................................................ 11
1.4 Related Products .......................................................................................................... 11
1.5 Document Conventions ................................................................................................... 11
1.6 Ordering Information ...................................................................................................... 11
1.7 Functional Block Diagram ................................................................................................ 12
1.8 Terminal Assignments .................................................................................................... 13
1.9 Terminal Functions ........................................................................................................ 14
2 Functional Description ....................................................................................................... 16
2.1 Analog Processing and A/D Converters ................................................................................ 16
2.1.1 Video Input Switch Control .................................................................................... 17
2.1.2 Analog Input Clamping ......................................................................................... 17
2.1.3 Automatic Gain Control ........................................................................................ 17
2.1.4 ADCs ............................................................................................................. 17
2.2 Digital Video Processing .................................................................................................. 17
2.2.1 2x Decimation Filter ............................................................................................ 18
2.2.2 Composite Processor .......................................................................................... 18
2.2.2.1 Color Low-Pass Filter .............................................................................. 20
2.2.2.2 Y/C Separation ..................................................................................... 21
2.2.3 Luminance Processing ......................................................................................... 22
2.2.4 Color Transient Improvement (CTI) .......................................................................... 22
2.2.5 Component Video Processor ................................................................................. 23
2.2.6 Color Space Conversion ....................................................................................... 23
2.3 Clock Circuits .............................................................................................................. 23
2.4 Real-Time Control (RTC) ................................................................................................. 24
2.5 Output Formatter .......................................................................................................... 25
2.5.1 Fast Switches for SCART ..................................................................................... 26
2.5.2 Separate Syncs ................................................................................................. 26
2.5.3 Embedded Syncs ............................................................................................... 31
2.6 I
2
C Host Interface .......................................................................................................... 32
2.6.1 Reset and I
2
C Bus Address Selection ....................................................................... 32
2.6.2 I
2
C Operation .................................................................................................... 32
2.6.3 VBUS Access ................................................................................................... 33
2.6.4 I
2
C Timing Requirements ...................................................................................... 34
2.7 VBI Data Processor ....................................................................................................... 34
2.7.1 VBI FIFO and Ancillary Data in Video Stream .............................................................. 35
2.7.2 VBI Raw Data Output .......................................................................................... 36
2.8 Reset and Initialization .................................................................................................... 36
2.9 Adjusting External Syncs ................................................................................................. 37
2.10 Internal Control Registers ................................................................................................ 38
2.11 Register Definitions ........................................................................................................ 42
2.12 VBUS Register Definitions ............................................................................................... 88
3 Electrical Specifications ..................................................................................................... 93
2 Contents Copyright © 2005–2012, Texas Instruments Incorporated
TVP5146M2
www.ti.com
SLES141H –JULY 2005– REVISED FEBRUARY 2012
3.1 Absolute Maximum Ratings .............................................................................................. 93
3.2 Recommended Operating Conditions .................................................................................. 93
3.3 Crystal Specifications ..................................................................................................... 93
3.4 Electrical Characteristics ................................................................................................. 94
3.5 DC Electrical Characteristics ............................................................................................. 94
3.6 Analog Processing and A/D Converters ................................................................................ 94
3.7 Clocks, Video Data, Sync Timing ....................................................................................... 95
3.8 I
2
C Host Port Timing ...................................................................................................... 95
3.9 Thermal Specifications .................................................................................................... 96
4 Example Register Settings .................................................................................................. 97
4.1 Example 1 .................................................................................................................. 97
4.1.1 Assumptions ..................................................................................................... 97
4.1.2 Recommended Settings ....................................................................................... 97
4.2 Example 2 .................................................................................................................. 98
4.2.1 Assumptions ..................................................................................................... 98
4.2.2 Recommended Settings ....................................................................................... 98
4.3 Example 3 .................................................................................................................. 99
4.3.1 Assumptions ..................................................................................................... 99
4.3.2 Recommended Settings ....................................................................................... 99
5 Application Information .................................................................................................... 100
5.1 Application Example ..................................................................................................... 100
5.2 Designing With PowerPAD™ Devices ................................................................................ 101
Revision History ....................................................................................................................... 102
Copyright © 2005–2012, Texas Instruments Incorporated Contents 3
TVP5146M2
SLES141H –JULY 2005– REVISED FEBRUARY 2012
www.ti.com
List of Figures
1-1 Functional Block Diagram ....................................................................................................... 13
1-2 Terminal Assignments Diagram ................................................................................................ 13
2-1 Analog Processors and A/D Converters ...................................................................................... 16
2-2 Digital Video Processing Block Diagram ...................................................................................... 18
2-3 Composite and S-Video Processor ............................................................................................ 19
2-8 Luminance Edge-Enhancer Peaking Block Diagram ........................................................................ 22
2-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling ............................................................ 22
2-10 Y Component Gain, Offset, Limit............................................................................................... 23
2-11 CbCr Component Gain, Offset, Limit .......................................................................................... 23
2-12 Reference Clock Configurations................................................................................................ 24
2-13 RTC Timing ....................................................................................................................... 24
2-14 Vertical Synchronization Signals for 525-Line System ...................................................................... 28
2-15 Vertical Synchronization Signals for 625-Line System ...................................................................... 29
2-16 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 30
2-17 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 31
2-18 VSYNC Position With Respect to HSYNC.................................................................................... 31
2-19 VBUS Access ..................................................................................................................... 34
2-20 Reset Timing...................................................................................................................... 37
2-21 Teletext Filter Function .......................................................................................................... 76
3-1 Clocks, Video Data, and Sync Timing ......................................................................................... 95
3-2 I
2
C Host Port Timing ............................................................................................................. 95
5-1 Example Application Circuit ................................................................................................... 100
4 List of Figures Copyright © 2005–2012, Texas Instruments Incorporated
TVP5146M2
www.ti.com
SLES141H –JULY 2005– REVISED FEBRUARY 2012
List of Tables
1-1 Terminal Functions............................................................................................................... 14
2-1 Output Format .................................................................................................................... 25
2-2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts....................................................... 25
2-3 EAV and SAV Sequence ........................................................................................................ 31
2-4 I
2
C Host Interface Terminal Description....................................................................................... 32
2-5 I
2
C Address Selection ........................................................................................................... 32
2-6 Supported VBI System .......................................................................................................... 34
2-7 Ancillary Data Format and Sequence ......................................................................................... 35
2-8 VBI Raw Data Output Format .................................................................................................. 36
2-9 Reset Sequence.................................................................................................................. 36
2-10 I
2
C Register Summary........................................................................................................... 38
2-11 VBUS Register Summary ....................................................................................................... 41
2-12 Input Select Register ............................................................................................................ 42
2-13 Analog Channel and Video Mode Selection .................................................................................. 42
2-14 AFE Gain Control Register ..................................................................................................... 43
2-15 Video Standard Register ....................................................................................................... 43
2-16 Operation Mode Control Register ............................................................................................. 44
2-17 Autoswitch Mask Register ...................................................................................................... 44
2-18 Color Killer Register ............................................................................................................. 45
2-19 Luminance Processing Control 1 Register ................................................................................... 45
2-20 Luminance Processing Control 2 Register ................................................................................... 46
2-21 Luminance Processing Control 3 Register ................................................................................... 46
2-22 Luminance Brightness Register ............................................................................................... 46
2-23 Luminance Contrast Register .................................................................................................. 47
2-24 Chrominance Saturation Register ............................................................................................. 47
2-25 Chroma Hue Register ........................................................................................................... 47
2-26 Chrominance Processing Control 1 Register ................................................................................ 48
2-27 Chrominance Processing Control 2 Register ................................................................................ 48
2-28 Component Pr Saturation Register ............................................................................................ 48
2-29 Component Y Contrast Register ............................................................................................... 49
2-30 Component Pb Saturation Register ........................................................................................... 49
2-31 Component Y Brightness Register ............................................................................................ 49
2-32 AVID Start Pixel Register ....................................................................................................... 50
2-33 AVID Stop Pixel Register ....................................................................................................... 50
2-34 HSYNC Start Pixel Register .................................................................................................... 50
2-35 HSYNC Stop Pixel Register .................................................................................................... 51
2-36 VSYNC Start Line Register .................................................................................................... 51
2-37 VSYNC Stop Line Register ..................................................................................................... 51
2-38 VBLK Start Line Register ....................................................................................................... 51
2-39 VBLK Stop Line Register ....................................................................................................... 52
2-40 Embedded Sync Offset Control 1 Register .................................................................................. 52
2-41 Embedded Sync Offset Control 2 Register .................................................................................. 52
2-42 Fast-Switch Control Register ................................................................................................... 53
2-43 Fast-Switch SCART Delay Register .......................................................................................... 53
2-44 SCART Delay Register ......................................................................................................... 53
2-45 CTI Delay Register .............................................................................................................. 54
2-46 CTI Control Register ............................................................................................................ 54
Copyright © 2005–2012, Texas Instruments Incorporated List of Tables 5
剩余107页未读，继续阅读
资源评论
不觉明了
- 粉丝: 3101
- 资源: 5337
上传资源 快速赚钱
我的内容管理
展开
- 我的资源
快来上传第一个资源
我的收益 登录查看自己的收益
我的积分
登录查看自己的积分
我的C币
登录后查看C币余额
我的收藏 
我的下载 
下载帮助
前往需求广场，查看用户热搜
安全验证
文档复制为VIP权益，开通VIP直接复制
信息提交成功