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TI-TVP5158.pdf
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TI-TVP5158.pdf
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TVP5158, TVP5157, TVP5156
Four-Channel NTSC/PAL Video Decoders
With Independent Scalers, Noise Reduction, Auto
Contrast, and Flexible Output Formatter for Security and
Other Multi-Channel Video Applications
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES243G
July 2009–Revised April 2013
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243G –JULY 2009–REVISED APRIL 2013
Contents
1 Introduction ........................................................................................................................ 8
1.1 Features ...................................................................................................................... 8
1.2 Applications .................................................................................................................. 9
1.3 Description ................................................................................................................... 9
1.4 Related Products ............................................................................................................ 9
1.5 Trademarks ................................................................................................................ 10
1.6 Document Conventions ................................................................................................... 10
1.7 Ordering Information ...................................................................................................... 10
1.8 Functional Block Diagram ................................................................................................ 11
2 Terminal Assignments ....................................................................................................... 12
2.1 Pinout ....................................................................................................................... 12
3 Functional Description ....................................................................................................... 15
3.1 Analog Video Processing and A/D Converters ........................................................................ 15
3.1.1 Analog Video Input ............................................................................................. 15
3.1.2 Analog Video Input Clamping ................................................................................. 16
3.1.3 A/D Converter ................................................................................................... 16
3.2 Digital Video Processing .................................................................................................. 16
3.2.1 2x Decimation Filter ............................................................................................ 16
3.2.2 Automatic Gain Control ........................................................................................ 16
3.2.3 Composite Processor .......................................................................................... 16
3.2.3.1 Color Low-Pass Filter .............................................................................. 17
3.2.3.2 Y/C Separation ..................................................................................... 18
3.2.4 Luminance Processing ......................................................................................... 19
3.3 AVID Cropping ............................................................................................................. 20
3.4 Embedded Syncs .......................................................................................................... 20
3.5 Scaler ....................................................................................................................... 21
3.6 Noise Reduction ........................................................................................................... 21
3.7 Auto Contrast .............................................................................................................. 21
3.8 Output Formatter .......................................................................................................... 22
3.8.1 Non-Interleaved Mode ......................................................................................... 22
3.8.2 Pixel-Interleaved Mode ......................................................................................... 22
3.8.2.1 2-Ch Pixel-Interleaved Mode ..................................................................... 23
3.8.2.2 4-Ch Pixel-Interleaved Mode ..................................................................... 23
3.8.2.3 Metadata Insertion for Non-Interleave Mode and Pixel-Interleaved Mode ................. 24
3.8.3 Line-Interleaved Mode Support (TVP5158 only) ........................................................... 25
3.8.3.1 2-Ch Line-Interleaved Mode ...................................................................... 25
3.8.3.2 4-Ch Line-Interleaved Mode ...................................................................... 26
3.8.3.3 8-Ch Line-Interleaved Mode ...................................................................... 26
3.8.3.4 Hybrid Modes ....................................................................................... 28
3.8.3.5 Metadata Insertion for Line-Interleaved Mode ................................................. 28
3.9 Audio Sub-System (TVP5157 and TVP5158 Only) ................................................................... 31
3.9.1 Features ......................................................................................................... 31
3.9.2 Audio Sub-System Functional Diagram ..................................................................... 32
3.9.3 Serial Audio Interface .......................................................................................... 33
3.9.4 Analog Audio Input Clamping ................................................................................. 33
3.9.5 Audio Cascade Connection ................................................................................... 34
3.10 I
2
C Host Interface .......................................................................................................... 36
3.10.1 I
2
C Write Operation ............................................................................................. 37
3.10.2 I
2
C Read Operation ............................................................................................ 37
3.10.3 VBUS Access ................................................................................................... 39
3.11 Clock Circuits .............................................................................................................. 40
2 Contents Copyright © 2009–2013, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243G –JULY 2009–REVISED APRIL 2013
3.12 Reset Mode ................................................................................................................ 41
4 Internal Control Registers ................................................................................................... 42
4.1 Overview .................................................................................................................... 42
4.2 Register Definitions ....................................................................................................... 45
5 Electrical Specifications ..................................................................................................... 90
5.1 Absolute Maximum Ratings .............................................................................................. 90
5.2 Recommended Operating Conditions .................................................................................. 91
5.3 Reference Clock Specifications ......................................................................................... 91
5.4 Electrical Characteristics ................................................................................................. 92
5.5 DC Electrical Characteristics ............................................................................................. 92
5.6 Video A/D Converters Electrical Characteristics ...................................................................... 93
5.7 Audio A/D Converters Electrical Characteristics ...................................................................... 93
5.8 Video Output Clock and Data Timing ................................................................................... 94
5.8.1 Video Input Clock and Data Timing .......................................................................... 94
5.9 I
2
C Host Port Timing ...................................................................................................... 95
5.9.1 I
2
S Port Timing .................................................................................................. 96
5.10 Miscellaneous Timings .................................................................................................... 96
5.11 Power Dissipation Ratings ............................................................................................... 96
6 Application Information ...................................................................................................... 97
6.1 4-Ch D1 Applications ..................................................................................................... 97
6.2 8-Ch CIF Applications ..................................................................................................... 97
6.3 16-Ch CIF Applications ................................................................................................... 98
6.4 Application Circuit Examples ............................................................................................. 99
6.5 Designing with PowerPAD™ Devices ................................................................................. 100
Revison History ........................................................................................................................ 101
Copyright © 2009–2013, Texas Instruments Incorporated Contents 3
TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013
www.ti.com
List of Figures
1-1 Functional Block Diagram ....................................................................................................... 11
3-1 Video Analog Processing and ADC Block Diagram ......................................................................... 15
3-2 Anti-Aliasing Filter Frequency Response ..................................................................................... 16
3-3 Composite Processor Block Diagram.......................................................................................... 17
3-4 Color Low-Pass Filter Frequency Response ................................................................................. 18
3-5 Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling................................. 18
3-6 Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling .............................................. 19
3-7 Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling ................................................ 19
3-8 Luminance Edge-Enhancer Peaking Block Diagram ........................................................................ 20
3-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling ............................................................ 20
3-10 2-Ch Pixel-Interleaved Mode Timing Diagram................................................................................ 23
3-11 4-Ch Pixel-Interleaved Mode Timing Diagram................................................................................ 24
3-12 Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview ............................................... 27
3-13 Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview........................................... 28
3-14 Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview..................................... 28
3-15 Start Code in 8-Bit BT.656 Interface........................................................................................... 29
3-16 Start Code in 16-Bit YCbCr 4:2:2 Interface ................................................................................... 30
3-17 Audio Sub-System Functional Diagram ....................................................................................... 33
3-18 Serial Audio Interface Timing Diagram ........................................................................................ 33
3-19 Audio Cascade Connection ..................................................................................................... 34
3-20 VBUS Access ..................................................................................................................... 39
3-21 Clock and Crystal Connectivity ................................................................................................. 40
3-22 Reset Timing...................................................................................................................... 41
5-1 Video Output Clock and Data Timing.......................................................................................... 94
5-2 I
2
C Host Port Timing ............................................................................................................. 95
6-1 4-Ch D1 Application (Single BT.656 Interface)............................................................................... 97
6-2 4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface) ......................................................................... 97
6-3 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application..................................................... 98
6-4 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application..................................................... 98
6-5 Video Input Connectivity ....................................................................................................... 100
6-6 Audio Input Connectivity ....................................................................................................... 100
4 List of Figures Copyright © 2009–2013, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243G –JULY 2009–REVISED APRIL 2013
List of Tables
1-1 Device Options ..................................................................................................................... 9
2-1 Terminal Functions .............................................................................................................. 13
3-1 EAV and SAV Sequence ........................................................................................................ 20
3-2 Standard Video Resolutions .................................................................................................... 21
3-3 Video Resolutions Converted by the Scaler .................................................................................. 21
3-4 Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards ................................. 22
3-5 Output Ports Configuration for Non-Interleaved Mode ...................................................................... 22
3-6 Output Ports Configuration for Pixel-Interleaved Mode ..................................................................... 23
3-7 VDET Statues Insertion in SAV/EAV Codes.................................................................................. 24
3-8 Channel ID Insertion in Horizontal Blanking Code........................................................................... 24
3-9 Channel ID Insertion in SAV/EAV Code Sequence.......................................................................... 24
3-10 Output Ports Configuration for Line-Interleaved Mode ...................................................................... 25
3-11 Default Super-Frame Format and Timing ..................................................................................... 29
3-12 Bit Assignment of 4-Byte Start Code for Active Video Line................................................................. 30
3-13 Bit Field Definition of 4-Byte Start Code for Active Video Line............................................................. 30
3-14 Bit Assignment of 4-Byte Start Code for the Dummy Line.................................................................. 31
3-15 Serial Audio Output Channel Assignment..................................................................................... 35
3-16 I
2
C Terminal Description ........................................................................................................ 36
3-17 I
2
C Host Interface Device Addresses.......................................................................................... 36
3-18 Reset Mode ....................................................................................................................... 41
3-19 Reset Sequence.................................................................................................................. 41
4-1 Registers Summary .............................................................................................................. 42
4-2 Status 1 ........................................................................................................................... 45
4-3 Status 2 ........................................................................................................................... 46
4-4 Color Subcarrier Phase Status ................................................................................................ 46
4-5 ROM Version ..................................................................................................................... 46
4-6 RAM Version MSB .............................................................................................................. 47
4-7 RAM Version LSB ............................................................................................................... 47
4-8 Chip ID MSB ..................................................................................................................... 47
4-9 Chip ID LSB ...................................................................................................................... 47
4-10 Video Standard Status .......................................................................................................... 48
4-11 Video Standard Select .......................................................................................................... 48
4-12 CVBS Autoswitch Mask ......................................................................................................... 49
4-13 Auto Contrast Mode ............................................................................................................. 49
4-14 Luminance Brightness .......................................................................................................... 49
4-15 Luminance Contrast ............................................................................................................. 50
4-16 Brightness and Contrast Range Extender .................................................................................... 50
4-17 Chrominance Saturation ........................................................................................................ 50
4-18 Chrominance Hue ............................................................................................................... 51
4-19 Color Killer ........................................................................................................................ 51
4-20 Luminance Processing Control 1 .............................................................................................. 52
4-21 Luminance Processing Control 2 .............................................................................................. 52
4-22 Power Control .................................................................................................................... 53
4-23 Chrominance Processing Control 1 ........................................................................................... 54
4-24 Chrominance Processing Control 2 ........................................................................................... 54
4-25 AGC Gain Status ................................................................................................................ 55
4-26 Back-End AGC Status .......................................................................................................... 55
Copyright © 2009–2013, Texas Instruments Incorporated List of Tables 5
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