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TVP5154A

www.ti.com

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

4-Channel Low-Power PAL/NTSC/SECAM Video Decoder

With Independent Scalers and Fast Lock

Check for Samples: TVP5154A

1 Introduction

1.1 Features

• Four Separate Video Decoder Channels With • Internal Phase-Locked Loop (PLL) for

Features for Each Channel: Line-Locked Clock (Separate for Each Channel)

and Sampling

– Accept NTSC (J, M, 4.43), PAL (B, D, G, H, I,

M, N, Nc), and SECAM (B, D, G, K, K1, L) • Sub-Carrier Genlock Output for Synchronizing

Video Color Sub-Carrier of External Encoder

– Support ITU-R BT.601 Standard Sampling • Standard Programmable Video Output Format

– High-Speed 9-Bit Analog-to-Digital Converter – ITU-R BT.656, 8-Bit 4:2:2 With Embedded

(ADC) Syncs

– Two Composite Inputs or One S-Video Input – 8-Bit 4:2:2 With Discrete Syncs

(for Each Channel)

• Advanced Programmable Video Output

– Fully Differential CMOS Analog Formats

Preprocessing Channels With Clamping and

– 2× Over-Sampled Raw Vertical Blanking

Automatic Gain Control (AGC) for Best

Interval (VBI) Data During Active Video

Signal to Noise (SNR) Performance

– Sliced VBI Data During Horizontal Blanking

– Brightness, Contrast, Saturation, Hue, and

or Active Video

Sharpness Control Through Inter-Integrated

• VBI Modes Supported:

Circuit (I

– Teletext (NABTS, WST)

– Complementary 4-Line (3-H Delay) Adaptive

– Closed-Caption Decode With FIFO, and

Comb Filters for Both Cross-Luminance and

Extended Data Services (EDS)

Cross-Chrominance Noise Reduction

– Wide Screen Signaling (WSS), Video

– Patented Architecture for Locking to Weak,

Program System (VPS), Copy Generation

Noisy, or Unstable Signals

Management System (CGMS), Vertical

• Four Independent Polymorphic Scalers

Interval Time Code (VITC)

• Single or Concurrent Scaled and Unscaled

– Gemstar 1×/2× Electronic Program Guide

Outputs Via Dual Clocking Data, Interleaved

Compatible Mode

54-MHz Data or Single 27-MHz Clock

– Custom Configuration Mode Allows User to

• Scaled/Unscaled Image Toggle Mode Gives

Program the Slice Engine for Unique VBI

Variable Field Rate for Both Scaled and

Data Signals

Unscaled Video

• Improved Fast Lock Mode Can Be Used When

• Low Power Consumption: 700 mW Typical

Input Video Standard Is Known and Signals on

• 128-Pin Thin Quad Flat Pack (TQFP) Package

Switching Channels Are Clean

• Single 14.31818-MHz Crystal for All Standards

• Four Possible I

C Addresses Allowing 16

and All Channels

Decoder Channels on a Single I

C Bus

• Available in Commercial (0°C to 70°C) and

Industrial (–40°C to 85°C) Temperature Ranges

1.2 Description

The TVP5154A device is a 4-channel, low-power, NTSC/PAL/SECAM video decoder. Available in a

space-saving 128-pin thin quad flat pack (TQFP) package, each channel of the TVP5154A decoder

converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

www.ti.com

available. All four channels of the TVP5154A are independently controllable. The decoders share one

crystal for all channels and for all supported standards. The TVP5154A can be programmed using a single

inter-integrated circuit (I

C) serial interface. The decoder uses a 1.8-V supply for its analog and digital

supplies, and a 3.3-V supply for its I/O. The optimized architecture of the TVP5154A decoder allows for

low power consumption. The decoder consumes less than 720 mW of power in typical operation.

Each channel of the TVP5154A is an independent video decoder with a programmable polymorphic

scaler. Each channel converts baseband analog video into digital YCbCr 4:2:2 component video, which

can then be scaled down to any resolution to 1/256 vertical and 15-bit horizontal in 2-pixel decrements.

Composite and S-video inputs are supported. Each channel includes one 9-bit analog-to-digital converter

(ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0) MHz, generated from a single 14.31818-MHz

crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 with discrete syncs or

8-bit ITU-R BT.656 with embedded synchronization.

The TVP5154A utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable

signals. A real-time control (RTC) output is generated for each channel for synchronizing downstream

video encoders.

Complementary 4-line adaptive comb filtering is available per channel for both the luma and chroma data

paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter also is available.

An improved fast lock mode can be used when the input video standard is known and the signals on the

switching channels are clean. Note, switching from snow and/or noisy channels to good channels takes

longer. In fast lock mode, video lock is achieved in three fields or less.

Video characteristics, including hue, contrast, brightness, saturation, and sharpness, may be

independently programmed for each channel using the industry standard I

C serial interface. The

TVP5154A generates synchronization, blanking, lock, and clock signals in addition to digital video outputs

for each channel. The TVP5154A includes methods for advanced vertical blanking interval (VBI) data

retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption,

and other data in several formats.

C commands can be sent to one or more decoder cores simultaneously, reducing the amount of I

activity necessary to configure each core. A register controls which decoder core receives I

C commands,

and can be configured such that all four decoders receive commands at the same time.

The main blocks for each of the channels of the TVP5154A decoder include:

• Robust sync detector

• ADC with analog processor

• Y/C separation using 4-line adaptive comb filter

• Independent, concurrent scaler outputs

• Chrominance processor

• Luminance processor

• Video clock/timing processor and power-down control

• I

C interface

• VBI data processor

1.3 Applications

• Security/Surveillance Digital Video Recorders/Servers and PCI Products

• Automotive Infotainment Video Hub

• Large-Format Video Wall Displays

• Games Systems

Submit Documentation Feedback

Product Folder Link(s): TVP5154A

TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

www.ti.com

1 Introduction .............................................. 1

3.15 Clock and Data Control ............................. 18

1.1 Features .............................................. 1 4 I

C Host Interface ...................................... 19

1.2 Description ........................................... 1 4.1 I

C Write Operation ................................. 20

4.2 I

C Read Operation ................................. 20

1.3 Applications .......................................... 2

5 Clock Circuits .......................................... 22

1.4 Related Products ..................................... 3

6 Genlock Control and RTC ........................... 23

1.5 Trademarks .......................................... 3

6.1 TVP5154A Genlock Control Interface .............. 23

1.6 Document Conventions .............................. 3

6.2 RTC Mode .......................................... 23

1.7 Ordering Information ................................. 3

6.3 Reset and Power Down ............................ 24

2 Device Details ............................................ 5

6.4 Reset Sequence .................................... 25

2.1 Functional Block Diagram ............................ 5

7 Internal Control Registers ........................... 26

2.2 Terminal Diagram .................................... 6

7.1 Overview ............................................ 26

2.3 Terminal Functions ................................... 7

7.2 Direct Register Definitions .......................... 29

3 Functional Description ................................. 9

7.3 Indirect Register Definitions ........................ 75

3.1 Analog Front End .................................... 9

8 Scaler Configuration .................................. 79

3.2 Composite Processing Block Diagram ............... 9

8.1 Overview ............................................ 79

3.3 Adaptive Comb Filtering ............................ 10

8.2 Horizontal Scaling .................................. 79

3.4 Color Low-Pass Filter ............................... 11

8.3 Vertical Scaling ..................................... 80

3.5 Luminance Processing ............................. 11

8.4 Field Interleaving ................................... 81

9 Electrical Specifications ............................. 82

3.6 Chrominance Processing ........................... 11

9.1 Absolute Maximum Ratings ........................ 82

3.7 Timing Processor ................................... 11

9.2 Recommended Operating Conditions .............. 82

3.8 VBI Data Processor ................................ 12

9.3 Reference Clock Specifications .................... 82

3.9 VBI FIFO and Ancillary Data in Video Stream ..... 13

9.4 Electrical Characteristics ........................... 83

3.10 Raw Video Data Output ............................ 14

9.5 Timing Requirements ............................... 84

3.11 Output Formatter ................................... 14

9.6 I

C Host Port Timing ................................ 85

3.12 Synchronization Signals ............................ 14

9.7 Thermal Specifications ............................. 85

3.13 Active Video (AVID) Cropping ...................... 15

10 Schematic ............................................... 86

3.14 Embedded Syncs ................................... 17

11 Revision History ....................................... 87

Submit Documentation Feedback

Product Folder Link(s): TVP5154A

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