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TI-TLV320AIC3120.pdf
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3120
SLAS653C –FEBRUARY 2010–REVISED FEBRUARY 2017
TLV320AIC3120 Low-Power Mono Audio Codec With Embedded miniDSP
and Mono Class-D Speaker Amplifier
1 Device Overview
1
1.1 Features
1
• Mono Audio DAC With 95-dB SNR
• Mono Audio ADC With 90-dB SNR
• Supports 8-kHz to 192-kHz Separate DAC and
ADC Sample Rates
• Instruction-Programmable Embedded miniDSP
• Mono Class-D BTL Speaker Driver (2.5 W Into 4 Ω
or 1.6 W Into 8 Ω) Output
• Mono Headphone/Lineout Outputs
• One Differential or Three Single-Ended Inputs With
Mixing and Level Control
• Microphone With Bias, Preamp PGA, and AGC
• Built-in Digital Audio Processing Blocks (PRB) With
User-Programmable Biquad, FIR Filters, and DRC
• Bass Boost/Treble/EQ With up to Five Biquads for
Record and up to Six Biquads for Playback
• Digital Mixing Capability
• Pin Control or Register Control for Digital Playback
Volume Control Settings
• Programmble PLL for Flexible Clock Generation
• I
2
S, Left-Justified, Right-Justified, DSP, and TDM
Audio Interfaces
• I
2
C Control With Register Auto-Increment
• Full Power-Down Control
• Power Supplies:
– Analog: 2.7 V–3.6 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
– Class-D: 2.7 V–5.5V (SPKVDD ≥ AVDD)
• 5-mm × 5-mm 32-QFN Package
1.2 Applications
• Portable Audio Devices
• Mobile Internet Devices
• eBooks
• Adaptive Filtering Applications
1.3 Description
The TLV320AIC3120 device is a low-power, highly integrated, high-performance codec which features a
mono audio DAC and mono audio ADC.
The TLV320AIC3120 device features a high-performance audio codec with 24-bit mono playback and
mono record functionality. The device integrates several analog features, such as a microphone interface,
headphone drivers, and speaker drivers. The TLV320AIC3120 device has a fully programmable miniDSP
for digital audio processing. The digital audio data format is programmable to work with popular audio
standard protocols (I
2
S, left-justified and right-justified) in master, slave, DSP, and TDM modes. Bass
boost, treble, or EQ are supported by the programmable digital signal-processing blocks (PRB). An on-
chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level is
controlled either by pin control or by register control. The audio functions are controlled using the I
2
C serial
bus.
The TLV320AIC3120 device is available in a 32-pin VQFN package.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV320AIC3120 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Audio Output Stage
Power Management
RC CLK
Digital
Audio
Processing
and
Serial
Interface
SDOUT
SDIN
BCLK
WCLK
MCLKPLL
7-Bit ADC P0/R117
Volume-Control Register
P0/R116
Digital Vol
24 dB to
Mute
P0/R64
miniDSP
Processing
Blocks
SPKP
SPKP
SPKM
SPKM
Class-D Speaker
Driver
6 dB to 24 dB (6-dB Steps)
Class A/B
Headphone/Lineout
Driver
0 dB to 9 dB (1-dB Steps)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
HPVDD
SPKVDD SPKVSS
AVDD
AVSSSPKVSSSPKVDD
VOL/
MICDET
HPOUT
SCL
SDA
GPIO GPIO1
MIX
MIX
MIC1LP
DAC
MIX
RESET
DVDD
DVSS
IOVDD IOVSS
OSC
RC CLK
MIC1LP
Selectable
Gain/Input
Impedance
VCOM
Selectable
Gain/Input
Impedance
P1/R47
0 to 59.5 dB
(0.5-dB steps)
AGC
MIC1RP
I C
2
2 V/2.5 V/AVDD
MICBIAS
Digital Vol
–12..20 dB
Step = 0.5 dB
Mono ADC
Note: Normally,
MCLK is PLL input;
however, BCLK
and GPIO1 can
also be PLL input.
D S-
ADC
D S-
DAC
De-Pop
and
Soft-
Start
P1/R33–R34
S
S
S
P1/R42
P1/R46
P1/R38
P1/R30
P1/R40
P1/R31
P1/R36
P0/R86–R93
P1/R48
P1/R49
Input CM
P1/R50
B0205-06
P0/R82–R83
HPVSS
MIC1RP
MIC1LM
Mono DAC
Digtal Mic
Interface
Clock
Data
Note: Digital Mic
Clock and Data
routed to GPIO1
and DIN pins.
P0/R51 and R54
L Data
L Data
R Data
(L + R)/2 Data
P0/R63
miniDSP
Processing
Blocks
Copyright © 2016, Texas Instruments Incorporated
2
TLV320AIC3120
SLAS653C –FEBRUARY 2010–REVISED FEBRUARY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: TLV320AIC3120
Device Overview Copyright © 2010–2017, Texas Instruments Incorporated
1.4 Functional Block Diagram
3
TLV320AIC3120
www.ti.com
SLAS653C –FEBRUARY 2010–REVISED FEBRUARY 2017
Submit Documentation Feedback
Product Folder Links: TLV320AIC3120
Revision HistoryCopyright © 2010–2017, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 3
3 Device Comparison ..................................... 5
4 Pin Configuration and Functions..................... 6
4.1 Pin Attributes ......................................... 6
5 Specifications ............................................ 8
5.1 Absolute Maximum Ratings .......................... 8
5.2 ESD Ratings.......................................... 8
5.3 Recommended Operating Conditions ................ 8
5.4 Thermal Information .................................. 9
5.5 Electrical Characteristics ............................. 9
5.6 Power Dissipation Ratings .......................... 11
5.7 I
2
S, LJF, and RJF Timing in Master Mode.......... 11
5.8 I
2
S, LJF, and RJF Timing in Slave Mode ........... 11
5.9 DSP Timing in Master Mode ........................ 11
5.10 DSP Timing in Slave Mode ......................... 12
5.11 I
2
C Interface Timing................................. 12
5.12 Typical Characteristics .............................. 15
6 Parameter Measurement Information .............. 19
7 Detailed Description ................................... 20
7.1 Overview ............................................ 20
7.2 Functional Block Diagram........................... 21
7.3 Feature Description ................................. 21
7.4 Register Map ........................................ 81
8 Application and Implementation................... 150
8.1 Application Information ............................ 150
8.2 Typical Application ................................. 150
9 Power Supply Recommendations................. 152
10 Layout................................................... 153
10.1 Layout Guidelines.................................. 153
10.2 Layout Example.................................... 153
11 Device and Documentation Support.............. 154
11.1 Receiving Notification of Documentation Updates. 154
11.2 Community Resources............................. 154
11.3 Trademarks ........................................ 154
11.4 Electrostatic Discharge Caution ................... 154
11.5 Glossary............................................ 154
12 Mechanical Packaging and Orderable
Information............................................. 154
12.1 Packaging Information ............................. 154
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2016) to Revision C Page
• Added: Page 0 / Register 51 (0x33): GPIO1 In/Out Pin Control .............................................................. 93
Changes from Revision A (May 2012) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section........................................... 1
• Deleted SPRVDD and SPRVSS pins from the Pin Functions table ........................................................... 6
• Changed references to SPLVDD in Typical Performance graphs to SPKVDD ............................................. 15
• Added Power-Supply Sequence section to the Device Initialization section ................................................ 21
• Added the reference to the PGA Gain Versus Input Impedance table in the MICBIAS and Microphone
Preamplifier section ................................................................................................................. 26
• Changed SDIN terminal to DIN in Figure 7-16 .................................................................................. 39
• Changed Section 7.3.12.1.2 diagrams for PRB_P2/5/8/10/13/15/18/21/24/25 to reflect that the DRC_HPF filter
cannot be bypassed when the DRC is turned off .............................................................................. 45
• Added sequence for inserting a beep in the middle of an already-playing signal and note text following script in
the Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) section........................................ 58
• Changed references of HPLOUT to HPOUT in Section 7.3.12.12.1 section................................................ 62
• Added PRB modes text to note for Page 0 / Register 20...................................................................... 86
• Added PRB modes text to Page 0 / Register 21. Also added Page 0 / Register 21 programmed value note.......... 86
• Added D(3:0) note to Page 0 / Register 22...................................................................................... 86
• Changed last line to "10111-11000: Reserved. Do not use." "11001: DAC Signal Processing Block PRB_P25"
"11010-11111: Reserved. Do not use." .......................................................................................... 94
• Changed values in Page 0 / Register 69 (0x45): DRC Control 2 ............................................................. 97
• Changed Page 0, Register 70, bit D3-D0 decay rate value for 0000 from DR = 1.5625e
–3
to DR = 0.015625 ........ 98
• Switched D1 and D0 descriptions so that D1 is for SP and D0 is for HP in Page 1 / Register 30 table ............... 105
4
TLV320AIC3120
SLAS653C –FEBRUARY 2010–REVISED FEBRUARY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: TLV320AIC3120
Revision History Copyright © 2010–2017, Texas Instruments Incorporated
• Changed Page 1 / Register 40, D1 to reserved ............................................................................... 107
• Changed references to TLV320AIC3111 device to the TLV320AIC3120 device throughout the REGISTER MAP
section .............................................................................................................................. 122
Changes from Original (February 2010) to Revision A Page
• Added PGA Gain table to data sheet............................................................................................. 26
• Added PRB_P25 and values to Table 7-20...................................................................................... 44
• Added Section 7.3.12.1.2.9 and Signal Chain with beep generator image.................................................. 46
• Added section Section 7.3.12.7 after Interrupts section ....................................................................... 57
• Added D6-D0 to the Register Value columns, and changed the Analog Attenuation columns to Analog Gain ........ 61
• Added table note to Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) table .................. 61
• Changed "page 0 / register 44" to " page 1 / register 44" in Headphone Drivers section ................................ 62
• Changed max AOSR values in Clock Distribution Tree image from 1023, 1024 to 255, 256............................. 67
• Changed PLL conditions under Equation 10 and Equation 11................................................................ 71
• Added Timer section................................................................................................................ 72
• Deleted the Page 0 / Register 71–Page 0 / Register 80 table and added Beep Generator bit registers from
SLAS659A (Page 0 / Register 71–80)............................................................................................ 98
• Modified Page 0 / Register 80 title from Page 0 / Register 80-115: Reserved to Page 0 / Register 80: Reserved. ... 99
• Corrected values in Description column for bits D6–D0 of Page 0 / Register 83 ......................................... 100
• Changed Bit D0 = 1 to Reserved. ............................................................................................... 106
• Deleted references to Analog Volume Control (D7 = 0) table from Page 1 / Register 36 and Page 1 / Register 38 107
• Changed Added table note following Page 1 / Register 40 .................................................................. 107
• Deleted one of the table notes from Page 1/ Register 48 and Page 1 / Register 49 ..................................... 109
• Deleted one of the table notes from Page 1/ Register 48 and Page 1 / Register 49 ..................................... 109
5
TLV320AIC3120
www.ti.com
SLAS653C –FEBRUARY 2010–REVISED FEBRUARY 2017
Submit Documentation Feedback
Product Folder Links: TLV320AIC3120
Device ComparisonCopyright © 2010–2017, Texas Instruments Incorporated
3 Device Comparison
Table 3-1. Device Features Comparison
FUNCTION TLV320AIC3100 TLV320AIC3110 TLV320AIC3111 TLV320AIC3120
DACs 2 2 2 1
ADCs 1 1 1 1
Inputs / Outputs 3/3 3/4 3/4 3/2
Resolution (Bits) 16, 20, 24, 32 16, 20, 24, 32 16, 20, 24, 32 16, 20, 24, 32
Control Interface I
2
C I
2
C I
2
C I
2
C
Digital Audio Interface LJ, RJ, I
2
S, TDM, DSP LJ, RJ, I
2
S, TDM, DSP LJ, RJ, I
2
S, TDM, DSP LJ, RJ, I
2
S, TDM, DSP
Number of Digital Audio Interfaces 1 1 1 1
Speaker Amplifier Type Mono Differential
Class-D
Stereo Differential
Class-D
Stereo Differential
Class-D
Mono Differential
Class-D
Configurable miniDSP No No Yes Yes
Headphone Driver Yes Yes Yes Yes
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