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Voltage

Controlled

Oscillator

Phase

Comparator

Phase

Comparator

Phase

Comparator

3COMP

SIG

2 PC1

OUT

PCP

OUT

5INH

VCO

OUT

7C1

9VCO

GND

11R

DEM

OUT

13 PC2

OUT

15 PC3

OUT

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LV4046A

SCES656E –FEBRUARY 2006–REVISED NOVEMBER 2016

SN74LV4046A High-Speed CMOS Logic Phase-Locked Loop With VCO

1 Features

• ESD Protection Exceeds JESD 22

– 2000-V Human Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

• Choice of Three Phase Comparators

– Exclusive OR

– Edge-Triggered J-K Flip-Flop

– Edge-Triggered RS Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for

Low Standby Power Consumption

• Optimized Power-Supply Voltage Range From

3 V to 5.5 V

• Wide Operating Temperature Range From

–40°C to +125°C

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

2 Applications

• Telecommunications

• Signal Generators

• Digital Phase-Locked Loop

3 Description

The SN74LV4046A is a high-speed silicon-gate

CMOS device that is pin compatible with the

CD4046B and the CD74HC4046. The device is

specified in compliance with JEDEC Std 7.

The SN74LV4046A is a phase-locked loop (PLL)

circuit that contains a linear voltage-controlled

oscillator (VCO) and three different phase

comparators (PC1, PC2, and PC3). A signal input

and a comparator input are common to each

comparator.

The signal input can be directly coupled to large

voltage signals, or indirectly coupled (with a series

capacitor) to small voltage signals. A self-bias input

circuit keeps small voltage signals within the linear

region of the input amplifiers. With a passive low-

pass filter, the SN74LV4046A forms a second-order

loop PLL. The excellent VCO linearity is achieved by

the use of linear operational amplifier techniques.

Various applications include telecommunications,

digital phase-locked loop and signal generators.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN74LV4046ANS SO (16) 7.70 mm × 10.20 mm

SN74LV4046AD SOIC (16) 6.00 mm × 9.90 mm

SN74LV4046APW TSSOP (16) 6.40 mm × 5.00 mm

SN74LV4046ADGVR TVSOP (16) 3.60 mm × 4.40 mm

SN74LV4046AN PDIP (16) 19.30 mm × 6.35 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

SN74LV4046A Functional Block Diagram

SN74LV4046A

SCES656E –FEBRUARY 2006–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: SN74LV4046A

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 6

6.7 Typical Characteristics.............................................. 9

7 Detailed Description............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 11

8 Application and Implementation ........................ 12

8.1 Application Information............................................ 12

8.2 Typical Application ................................................. 12

9 Power Supply Recommendations...................... 14

10 Layout................................................................... 14

10.1 Layout Guidelines ................................................. 14

10.2 Layout Example .................................................... 14

11 Device and Documentation Support ................. 15

11.1 Documentation Support ........................................ 15

11.2 Receiving Notification of Documentation Updates 15

11.3 Community Resources.......................................... 15

11.4 Trademarks........................................................... 15

11.5 Electrostatic Discharge Caution............................ 15

11.6 Glossary................................................................ 15

12 Mechanical, Packaging, and Orderable

Information ........................................................... 15

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (September 2015) to Revision E Page

• Deleted 200-V Machine Model (A115-A) from Features ........................................................................................................ 1

• Added TVSOP and PDIP packages to Device Information table........................................................................................... 1

• Added TVSOP, SO, and PDIP packages to pinout................................................................................................................ 3

• Changed R

θJA

for D package from 73°C/W to 82.8°C/W........................................................................................................ 4

• Changed R

θJA

for DGV package from 120°C/W to 116.8°C/W .............................................................................................. 4

• Changed R

θJA

for NS package from 64°C/W to 83.5°C/W ..................................................................................................... 4

• Changed R

θJA

for PW package from 108°C/W to 108.1°C/W ................................................................................................ 4

• Added values in the Thermal Information table to align with JEDEC standards ................................................................... 4

• Changed x-axis from "–360° 0° 360°" to "0° 90° 180°" ......................................................................................................... 9

• Changed "(V

/4)" to "(V

/4π)".............................................................................................................................................. 9

• Added Receiving Notification of Documentation Updates section ....................................................................................... 15

Changes from Revision C (April 2007) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

SN74LV4046A

SCES656E –FEBRUARY 2006–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: SN74LV4046A

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

DC supply voltage –0.5 7 V

Input voltage –0.5 V

+ 0.5 V

Output voltage –0.5 V

+ 0.5 V

Input clamp current V

< 0 –20 mA

Output clamp current V

< 0 –50 mA

Continuous output curent V

= 0 to V

±35 mA

DC V

or ground current ±70 mA

Junction temperature 150 °C

stg

Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101

(2)

±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Operating free-air temperature –40 125 °C

Supply voltage 3 5.5 V

, V

DC input or output voltage 0 V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC

(1)

SN74LV4046A

UNITD (SOIC) DGV (TVSOP) NS (SO) PW (TSSOP) N (PDIP)

16 PINS 16 PINS 16 PINS 16 PINS 16 PINS

θJA

Junction-to-ambient thermal

resistance

82.8 116.8 83.5 108.1 49.4 °C/W

θJC(top)

Junction-to-case (top) thermal

resistance

44.0 43.3 41.7 42.7 36.7 °C/W

θJB

Junction-to-board thermal resistance 40.3 48.3 43.8 53.1 29.3 °C/W

Junction-to-top characterization

parameter

11.1 3.7 9.3 4.2 21.5 °C/W

Junction-to-board characterization

parameter

40.0 47.8 43.5 52.5 29.2 °C/W

SN74LV4046A

www.ti.com

SCES656E –FEBRUARY 2006–REVISED NOVEMBER 2016

Product Folder Links: SN74LV4046A

(1) The value for R1 and R2 in parallel should exceed 2.7 kΩ.

(2) The maximum operating voltage can be as high as V

– 0.9 V; however, this may result in an increased offset voltage.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

(V) MIN TYP MAX UNIT

(V) I

(mA)

VCO

High-level input voltage INH

3 to 3.6 V

× 0.7

4.5 to 5.5 V

× 0.7

Low-level input voltage INH

3 to 5.5 V

× 0.3

4.5 to 5.5 V

× 0.3

High-level

output voltage

VCO

OUT

CMOS

or V

–0.05

3 to 3.6 V

– 0.1

V4.5 to 5.5 V

– 0.1

TTL –12 4.5 to 5.5 3.8

Low-level

output voltage

VCO

OUT

CMOS

or V

0.05

3 to 3.6 0.1

4.5 to 5.5 0.1

TTL 12 4.5 to 5.5 0.55

C1A, C1B

(test purposes only)

12 4.5 to 5.5 0.65

Input leakage current INH, VCO

or GND 5.5 ±1 μA

R1 range

(1)

3 to 5.5 3 50 kΩ

R2 range

(1)

3 to 5.5 3 50 kΩ

C1 capacitance range

3 to 3.6 40 No Limit

4.5 to 5.5 40 No Limit

Operating voltage range VCO

Over the range specified for

R1 for linearity

(2)

3 to 3.6 1.1 1.9

4.5 to 5.5 1.1 3.2

PHASE COMPARATOR

DC-coupled high-level

input voltage

SIG

COMP

3 to 3.6 V

× 0.7

4.5 to 5.5 V

× 0.7

DC-coupled low-level input voltage

SIG

COMP

3 to 3.6 V

× 0.3

4.5 to 5.5 V

× 0.3

High-level

output voltage

PCP

OUT

PCN

OUT

CMOS

or V

–0.05 3 to 5.5 V

– 0.1

V–6 3 to 3.6 2.48

TTL –12 4.5 to 5.5 3.8

Low-level

output voltage

PCP

OUT

PCN

OUT

CMOS

or V

0.02

3 to 3.6 0.1

4.5 to 5.5 0.1

4 4.5 to 5.5 0.4

TTL

Input leakage current

SIG

COMP

or GND

3 to 3.6 ±11

μA

4.5 to 5.5 ±29

3-state off-state current PC2

OUT

or V

3 to 5.5 ±5 μA

Input resistance

SIG

COMP

at self-bias operating

point, V

= 0.5 V

3 800

kΩ

4.5 250

DEMODULATOR

Resistor range

> 300 kΩ, Leakage

current can influence

DEMOUT

3 to 3.6 50 300

kΩ

4.5 to 5.5 50 300

OFF

Offset voltage VCO

to V

DEM

= V

VCOIN

= V

CC/2

, Values

taken over R

range

3 to 3.6 ±30

4.5 to 5.5 ±20

Quiescent device current

Pins 3, 5, and 14 at V

Pin 9 at GND, I

at pins 3

and 14 to be excluded

5.5 50 μA

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