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TI-SN74LV221A是一款由德州仪器（Texas Instruments）生产的数字集成电路，它是一款四路双稳态触发器，适用于各种电子系统中的定时和数据存储应用。这款芯片的特点在于其兼容广泛的电源电压范围（2V到5.5V），这使得它能够支持混合模式电压操作，即在所有端口上可以处理不同电压等级的信号。该器件的主要功能包括： 1. **Schmitt-Trigger输入**：A、B和CLR输入端采用了Schmitt-Trigger电路，这种电路设计能提高输入信号的抗干扰能力，即使输入信号变化缓慢也能保证稳定的工作状态。 2. **快速响应时间**：在5V电源下，最大传播延迟（tpd）仅为11ns，这表明SN74LV221A具有快速的信号处理能力。 3. **清除功能**：提供了一个可覆盖的清除（Clear）输入，当清除信号有效时，无论其他输入状态如何，输出都会被终止，确保输出脉冲的精确控制。 4. **上电复位**：SN74LV221A在电源开启时，其输出会进行无毛刺的复位，保证系统启动时的稳定性。 5. **部分电源关闭模式支持**：通过Ioff特性，芯片可以在部分电源关闭模式下工作，降低功耗，同时不会损坏内部电路。 6. **抗闩锁性能**：根据JESD 78，Class II标准，该器件的抗闩锁性能超过了100mA，确保了在高电流冲击下的稳定性。 7. **静电放电保护**：SN74LV221A提供了超过JESD 22规定的静电放电保护标准，包括2000V的人体模型（A114-A）、200V的机器模型（A115-A）和1000V的充电设备模型（C101），增强了在操作和储存过程中的安全性。 8. **封装选项**：该芯片提供了多种封装形式，如SOIC（小外形集成电路）、SOP（小外形封装）、TSSOP（薄型小外形封装）、DIP（双列直插封装）和FK封装等，满足不同应用环境的需求。 9. **温度范围**：根据不同的封装类型，SN74LV221A可在-40°C至85°C或-55°C至125°C的温度范围内正常工作。在订购时，用户可以根据需要选择不同的封装类型，例如SN74LV221AD是D封装，适合小批量购买；而SN74LV221AWS则适合在-55°C至125°C的宽温环境下使用。完整的订购信息包括器件型号、封装类型、订单零件编号以及顶部标记等。总体来说，TI-SN74LV221A是一款高性能、多功能的双稳态触发器，适用于需要高速、低功耗、高可靠性的电子系统设计。在设计电路时，用户应参考提供的封装信息，考虑温度范围、电源电压、抗静电保护和抗闩锁性能等因素，确保芯片能在实际应用中发挥最佳性能。

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  

SCLS450G − DECEMBER 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 11 ns at 5 V

D Support Mixed-Mode Voltage Operation on

All Ports

D Schmitt-Trigger Circuitry on A, B, and CLR

Inputs for Slow Input Transition Rates

D Overriding Clear Terminates Output Pulse

D Glitch-Free Power-Up Reset on Outputs

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV221A ...J OR W PACKAGE

SN74LV221A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV221A . . . FK PACKAGE

(TOP VIEW)

1CLR

ext

GND

ext

2CLR

3212019

910111213

ext

2CLR

1CLR

ext

GND

NC − No internal connection

ext

description/ordering information

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV221AD

LV221A

SOIC − D

Reel of 2500 SN74LV221ADR

LV221A

SOP − NS Reel of 2000 SN74LV221ANSR 74LV221A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV221ADBR LV221A

−40°C to 85°C

Tube of 90 SN74LV221APW

TSSOP − PW

Reel of 2000 SN74LV221APWR

LV221A

TSSOP − PW

Reel of 250 SN74LV221APWT

LV221A

TVSOP − DGV Reel of 2000 SN74LV221ADGVR LV221A

CDIP − J Tube of 25 SNJ54LV221AJ SNJ54LV221AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV221AW SNJ54LV221AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV221AFK SNJ54LV221AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V V

operation. Each multivibrator has

a negative-transition-triggered (A

) input and a positive-transition-triggered (B) input, either of which can be used

as an inhibit input.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,

the A

input is low and the B input goes high. In the second method, the B input is high and the A input goes low.

In the third method, the A

input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The

external timing capacitor must be connected between C

ext

and R

ext

(positive) and an external resistor

connected between R

ext

and V

. To obtain variable pulse durations, connect an external variable resistor

between R

ext

and V

. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input

pulse. The A

, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition

rates with jitter-free triggering at the outputs.

Once triggered, the outputs are independent of further transitions of the A

and B inputs and are a function of

the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of

any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing

components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering

and clearing sequences are illustrated in the input/output timing diagram.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing

components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse

duration versus supply voltage and temperature are shown in Figure 5.

During power up, Q outputs are in the low state, and Q

outputs are in the high state. The outputs are glitch free,

without applying a reset pulse.

These devices are fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the

outputs, preventing damaging current backflow through the devices when they are powered down.

Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be

substituted for those devices not using the retrigger feature.

For additional application information on multivibrators, see the application report Designing With The

SN74AHC123A and SN74AHCT123A, literature number SCLA014.

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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range in high or low state, V

(see Notes 1 and 2) −0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . .

Output voltage range in power-off state, V

(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

= 0 to V

) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

 

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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

SN54LV221A SN74LV221A

UNIT

MIN MAX MIN MAX

UNIT

Supply voltage 2 5.5 2 5.5 V

= 2 V 1.5 1.5

High-level input voltage

= 2.3 V to 2.7 V V

× 0.7 V

× 0.7

High-level input voltage

= 3 V to 3.6 V

× 0.7 V

× 0.7

= 4.5 V to 5.5 V V

× 0.7 V

× 0.7

= 2 V 0.5 0.5

Low-level input voltage

= 2.3 V to 2.7 V V

× 0.3 V

× 0.3

Low-level input voltage

= 3 V to 3.6 V

× 0.3 V

× 0.3

= 4.5 V to 5.5 V V

× 0.3 V

× 0.3

Input voltage 0 5.5 0 5.5 V

Output voltage 0 V

0 V

= 2 V −50 −50 µA

High-level output current

= 2.3 V to 2.7 V −2 −2

High-level output current

= 3 V to 3.6 V

−6 −6

= 4.5 V to 5.5 V −12 −12

= 2 V 50 50 µA

Low-level output current

= 2.3 V to 2.7 V 2 2

Low-level output current

= 3 V to 3.6 V

6 6

= 4.5 V to 5.5 V 12 12

ext

External timing resistance

= 2 V 5k 5k

Ω

ext

External timing resistance

≥ 3 V

1k 1k

Ω

ext

External timing capacitance No restriction No restriction pF

∆t/∆V

Power-up ramp rate 1 1 ms/V

Operating free-air temperature −55 125 −40 85 °C

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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