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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS691

LMK62E2-100M

LMK62E2-156M

LMK62E0-156M

LMK62A2-100M

LMK62A2-150M

LMK62A2-156M

LMK62A2-200M

LMK62A2-266M

LMK62I0-100M

LMK62I0-156M

ZHCSGL2D –DECEMBER 2016–REVISED JULY 2018

LMK62XX 高高性性能能低低抖抖动动振振荡荡器器

1 特特性性

• 低噪声，高性能

– 抖动：Fout > 100MHz 时的典型值为 150fs

(RMS)

– 电源抑制比 (PSRR)：-60dBc，出色的电源抗扰

度

• 支持的输出格式

– 低压正发射极耦合逻辑 (LVPECL)、低压差分信

令 (LVDS) 和高速收发器逻辑 (HCSL) 高达

400MHz

• 总频率容差为 ±50ppm (LMK62X2) 和 ±25ppm

(LMK62X0)

• 3.3V 工作电压

• 工业温度范围（-40ºC 至 +85ºC）

• 5mm × 3.2mm 6 引脚封装，与行业标准 5032 XO

封装引脚兼容

2 应应用用

• 晶体振荡器、表面声波 (SAW) 振荡器或芯片振荡

器的高性能替换产品

• 开关、路由器、网卡、基带装置 (BBU)、服务器、

存储/SAN

• 测试和测量

• 医疗成像

• FPGA，处理器连接

3 说说明明

LMK62XX 器件是一款低抖动振荡器，可生成常用参考

时钟。该器件在工厂预编程，可支持任何参考时钟频

率；支持的输出格式是 LVPECL、LVDS 和 HCSL

（最高 400MHz）。内部电源调节功能提供出色的电

源纹波抑制 (PSRR)，降低了供电网络的成本和复杂

性。该器件由单个 3.3V ± 5% 电源供电。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

LMK62E2-100M QFM (6) 5.00mm × 3.20mm

LMK62E2-156M QFM (6) 5.00mm × 3.20mm

LMK62E0-156M QFM (6) 5.00mm × 3.20mm

LMK62A2-100M QFM (6) 5.00mm × 3.20mm

LMK62A2-150M QFM (6) 5.00mm × 3.20mm

LMK62A2-156M QFM (6) 5.00mm × 3.20mm

LMK62A2-200M QFM (6) 5.00mm × 3.20mm

LMK62A2-266M QFM (6) 5.00mm × 3.20mm

LMK62I0-100M QFM (6) 5.00mm × 3.20mm

LMK62I0-156M QFM (6) 5.00mm × 3.20mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

输输出出频频率率选选项项

器器件件型型号号

输输出出频频率率 (MHz) 及及格格

式式

总总频频率率稳稳定定性性 (ppm)

LMK62E2-100M 100 LVPECL ±50

LMK62E2-156M 156.25 LVPECL ±50

LMK62E0-156M 156.25 LVPECL ±25

LMK62A2-100M 100 LVDS ±50

LMK62A2-150M 150 LVDS ±50

LMK62A2-156M 156.25 LVDS ±50

LMK62A2-200M 200 LVDS ±50

LMK62A2-266M 266.66 LVDS ±50

LMK62I0-100M 100 HCSL ±25

LMK62I0-156M 156.25 HCSL ±25

引引脚脚分分配配

LMK62E2-100M

LMK62E2-156M

LMK62E0-156M

LMK62A2-100M

LMK62A2-150M

LMK62A2-156M

LMK62A2-200M

LMK62A2-266M

LMK62I0-100M

LMK62I0-156M

ZHCSGL2D –DECEMBER 2016–REVISED JULY 2018

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings ............................................................ 3

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics - Power Supply ................. 4

6.6 LVPECL Output Characteristics................................ 4

6.7 LVDS Output Characteristics .................................... 5

6.8 HCSL Output Characteristics.................................... 5

6.9 OE Input Characteristics........................................... 5

6.10 Frequency Tolerance Characteristics ..................... 5

6.11 Power-On/Reset Characteristics (VDD).................. 6

6.12 PSRR Characteristics ............................................. 6

6.13 PLL Clock Output Jitter Characteristics .................. 6

6.14 Additional Reliability and Qualification.................... 6

7 Parameter Measurement Information .................. 7

7.1 Device Output Configurations................................... 7

8 Power Supply Recommendations........................ 9

9 Layout ..................................................................... 9

9.1 Layout Guidelines ..................................................... 9

10 器器件件和和文文档档支支持持 ..................................................... 11

10.1 接收文档更新通知 ................................................. 11

10.2 社区资源................................................................ 11

10.3 商标 ....................................................................... 11

10.4 静电放电警告......................................................... 11

10.5 术语表 ................................................................... 11

11 机机械械、、封封装装和和可可订订购购信信息息....................................... 12

4 修修订订历历史史记记录录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (December 2017) to Revision D Page

• Added V

minimum and maximum values to the LVDS Output Characteristics table ......................................................... 5

Changes from Revision B (June 2017) to Revision C Page

• 在器件列表中增加了 LMK62E2-100M、LMK62I0-100M 和 LMK62I0-156M.......................................................................... 1

Changes from Revision A (April 2017) to Revision B Page

• 在器件列表中增加了 LMK62E0-156M、LMK62A2-100M、LMK62A2-150M、LMK62A2-156M、LMK62A2-200M 和

LMK62A2-266M...................................................................................................................................................................... 1

Changes from Original (December 2016) to Revision A Page

• 已更新生产数据的高级信息产品说明书................................................................................................................................... 1

LMK62E2-100M

LMK62E2-156M

LMK62E0-156M

LMK62A2-100M

LMK62A2-150M

LMK62A2-156M

LMK62A2-200M

LMK62A2-266M

LMK62I0-100M

LMK62I0-156M

ZHCSGL2D –DECEMBER 2016–REVISED JULY 2018

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDD Device supply voltage 3.135 3.3 3.465 V

Ambient temperature –40 25 85 °C

Junction temperature 105 °C

RAMP

VDD power-up ramp time 0.1 100 ms

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal resistance is calculated on a 4-layer JEDEC board.

(3) Connected to GND with 2 thermal vias (0.3-mm diameter).

(4) ψ

(junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations

section for more information on ensuring good system reliability and quality.

6.4 Thermal Information

THERMAL METRIC

(1)

LMK62XX

(2) (3) (4)

UNIT

SIA (QFM )

6 PINS

Airflow (LFM) 0

θJA

Junction-to-ambient thermal resistance 94.5 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 65.1 °C/W

θJB

Junction-to-board thermal resistance 59 °C/W

Junction-to-top characterization parameter 23.3 °C/W

Junction-to-board characterization parameter 64.1 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance n/a °C/W

(1) See Parameter Measurement Information for relevant test conditions.

(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.

(3) Excludes load current.

6.5 Electrical Characteristics - Power Supply

VDD = 3.3 V ± 5%, T

= –40°C to 85° C

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IDD Device current consumption

LVPECL

(2)

95 110

mALVDS 85 100

HCSL

(3)

90 105

IDD-PD

Device current consumption

when output is disabled

OE = GND 70 mA

(1) See Parameter Measurement Information for relevant test conditions.

(2) An output frequency over f

OUT

max spec is possible, but output swing may be less than V

min spec.

(3) Ensured by characterization.

6.6 LVPECL Output Characteristics

VDD = 3.3 V ± 5%, T

= –40°C to 85° C

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUT

Output frequency

(2)

400 MHz

Output voltage swing (V

– V

)

(2)

700 950 1200 mV

OUT, DIFF, PP

Differential output peak-to-peak swing 2 × |V

| V

Output common-mode voltage VDD – 1.45 V

/ t

Output rise/fall time (20% to 80%)

(3)

260 350 ps

ODC Output duty cycle

(3)

45% 55%

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