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ADD OUT1

VDDOE

GND OUT0

SCL

SDA

1 6

2 5

LMK61E0X

Ultra-high performance oscillator

PLL

Output

Divider

Output

Buffer

Power

Conditioning

Interface

C/EEPROM

Integrated

Oscillator

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Folder

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS692

LMK61E0M

ZHCSG16A –JANUARY 2017–REVISED MAY 2017

具具有有内内部部 EEPROM 的的 LMK61E0M 超超低低抖抖动动可可编编程程振振荡荡器器

1 特特性性

• 超低噪声、高性能

– 抖动：500fs RMS 典型值（在 LMK61E0M

上，f

OUT

> 50 MHz）

• LMK61E0M 支持高达 200MHz 的 3.3V LVCMOS

输出

• 总频率容差：±25ppm

• 系统级特性

– 无毛刺频率裕量：与标称值相差最多

±1000ppm

– 内部 EEPROM：用户可配置的启动设置

• 其他特性

– 器件控制：快速模式 I

C 高达 1000kHz

– 3.3V 工作电压

– 工业温度范围（-40ºC 至 +85ºC）

– 7mm × 5mm 8 引脚封装

• 默认频率：70.656MHz

2 应应用用

• 晶体振荡器、SAW 振荡器或芯片振荡器的高性能

替代产品

• 开关、路由器、网卡、基带装置 (BBU)、服务器、

存储/SAN

• 测试和测量

• 医疗成像

• FPGA，处理器连接

• xDSL，广播视频

3 说说明明

LMK61E0 系列超低抖动 PLLatinum

可编程振荡器

使用分数 N 频率合成器与集成 VCO 来生成常用的参

考时钟。LMK61E0M 支持 3.3V LVCMOS 输出。该器

件具有从片上 EEPROM 自启动的功能以便产生出厂

设置的默认输出频率，或者可通过 I

C 串行接口在系统

中对器件寄存器和 EEPROM 设置进行完全编程。该器

件通过 I

C 串行接口提供精细和粗糙的频率裕量控制，

因此成为一种数控振荡器 (DCXO)。

您可以更新 PLL 反馈分频器，从而使用 12.5MHz 的

PFD（R 分频器=4，禁用倍频器）以小于 1ppb 的步进

值进行无峰值或毛刺的输出频率调节以符合 xDSL 要

求，或使用 100MHz 的 PFD（R 分频器=1，启用倍频

器）以小于 5.2ppb 的步进值进行此调节以符合广播视

频要求。频率裕量特性也有利于进行系统设计验证测

试 (DVT)，如标准合规性和系统时序裕量测试。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

LMK61E0M QFM (8) 7.00mm x 5.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

引引脚脚分分布布和和简简化化框框图图

LMK61E0M

ZHCSG16A –JANUARY 2017–REVISED MAY 2017

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics - Power Supply ................. 4

6.6 3.3-V LVCMOS Output Characteristics..................... 4

6.7 OE Input Characteristics........................................... 5

6.8 ADD Input Characteristics......................................... 5

6.9 Frequency Tolerance Characteristics ....................... 5

6.10 Frequency Margining Characteristics ..................... 5

6.11 Power-On/Reset Characteristics (VDD).................. 6

6.12 I

C-Compatible Interface Characteristics (SDA,

SCL)........................................................................... 6

6.13 Other Characteristics .............................................. 6

6.14 PLL Clock Output Jitter Characteristics .................. 6

6.15 Additional Reliability and Qualification.................... 7

6.16 Typical Characteristics............................................ 7

7 Parameter Measurement Information .................. 8

7.1 Device Output Configurations................................... 8

8 Detailed Description.............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ......................................... 9

8.3 Feature Description................................................... 9

8.4 Device Functional Modes........................................ 13

8.5 Programming........................................................... 16

8.6 Register Maps......................................................... 20

9 Application and Implementation ........................ 35

9.1 Application Information............................................ 35

9.2 Typical Application .................................................. 35

10 Power Supply Recommendations ..................... 40

11 Layout................................................................... 40

11.1 Layout Guidelines ................................................. 40

11.2 Layout Example .................................................... 41

12 器器件件和和文文档档支支持持 ..................................................... 42

12.1 文档支持 ............................................................... 42

12.2 接收文档更新通知 ................................................. 42

12.3 社区资源................................................................ 42

12.4 商标 ....................................................................... 42

12.5 静电放电警告......................................................... 42

12.6 Glossary................................................................ 42

13 机机械械、、封封装装和和可可订订购购信信息息....................................... 42

4 修修订订历历史史记记录录

Changes from Original (January 2017) to Revision A Page

• 根据最新文档和翻译标准更新了产品说明书文本 .................................................................................................................... 1

• Corrected recommended junction temperature ..................................................................................................................... 4

• Corrected junction temperature ............................................................................................................................................. 5

• Updated register names ....................................................................................................................................................... 20

• Typical application schematic added ................................................................................................................................... 35

LMK61E0M

ZHCSG16A –JANUARY 2017–REVISED MAY 2017

www.ti.com.cn

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101

(2)

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDD Device supply voltage 3.135 3.3 3.465 V

Ambient temperature –40 25 85 °C

Junction temperature 115 °C

RAMP

VDD power-up ramp time 0.1 100 ms

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal resistance is calculated on a 4-layer JEDEC board.

(3) Connected to GND with 3 thermal vias (0.3-mm diameter).

(4) ψ

(junction-to-board) is used when the main heat flow is from the junction to the GND pad. See Layout Guidelines for more information

on ensuring good system reliability and quality.

6.4 Thermal Information

THERMAL METRIC

(1)

LMK61E0

(2) (3) (4)

UNIT

SIA (QFM)

8 PINS

Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400

θJA

Junction-to-ambient thermal resistance 54 44 41.2 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 34 n/a n/a °C/W

θJB

Junction-to-board thermal resistance 36.7 n/a n/a °C/W

Junction-to-top characterization parameter 11.2 16.9 21.9 °C/W

Junction-to-board characterization parameter 36.7 37.8 38.9 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W

(1) Refer to Parameter Measurement Information for relevant test conditions.

6.5 Electrical Characteristics - Power Supply

(1)

VDD = 3.3 V ± 5%, T

= –40°C to 85° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IDD Device current consumption LVCMOS 140 180 mA

IDD-PD Device current consumption

when output is disabled

OE = GND 120 mA

(1) Refer to Parameter Measurement Information for relevant test conditions.

6.6 3.3-V LVCMOS Output Characteristics

(1)

VDD = 3.3 V ± 5%, T

= –40°C to 85° C, outputs loaded with 2 pF to GND

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUT

Output frequency Fast mode, R22[7:6] = 0x0 50 200 MHz

Output high voltage I

= 1 mA 2.5 V

Output low voltage I

= 1 mA 0.6 V

Output high current –33 mA

Output low current 33 mA

剩余47页未读，继续阅读

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