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TI-LMK61E07.pdf
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SCL OUTN
VDDSDA
GND OUTP
1 6
2 5
43
LMK61E0X
Ultra-high performance oscillator
PLL
Output
Divider
Output
Buffer
Power
Conditioning
Interface
I
2
C/EEPROM
Integrated
Oscillator
Copyright © 2016, Texas Instruments Incorporated
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Folder
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本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS722
LMK61E07
ZHCSH74A –DECEMBER 2017–REVISED OCTOBER 2018
具具有有内内部部 EEPROM 的的 LMK61E07 超超低低抖抖动动可可编编程程振振荡荡器器
1
1 特特性性
1
• 超低噪声、高性能
– 抖动:90fs RMS 典型值(在 LMK61E07
上,f
OUT
> 100MHz)
– PSRR:–70dBc,LMK61E07 具有强大的抗电
源噪声能力
• LMK61E07 具有灵活的输出格式
– LVPECL 高达 1 GHz
– LVDS 高达 900 MHz
– HSTL 高达 400 MHz
• 总频率容差:±25 ppm
• 系统级 特性
– 无毛刺频率裕量:与标称值相差最多
±1000ppm
– 内部 EEPROM:用户可配置的启动设置
• 其他 特性
– 器件控制:快速模式 I
2
C 高达 1000kHz
– 3.3V 工作电压
– 工业温度范围(-40ºC 至 +85ºC)
– 7mm × 5mm 8 引脚封装
• 默认频率:
– 70.656MHz
2 应应用用
• 晶体振荡器、SAW 振荡器或芯片振荡器的高性能
替代产品
• 开关、路由器、网卡、基带装置 (BBU)、服务器、
存储/SAN
• 测试和测量
• 医疗成像
• FPGA,处理器连接
• xDSL,广播视频
3 说说明明
LMK61E07 系列超低抖动 PLLatinum
TM
可编程振荡器
使用分数 N 频率合成器与集成 VCO 来生成常用的参
考时钟。LMK61E07 的输出可配置为 LVPECL、
LVDS、或 HCSL。该器件 具有 从片上 EEPROM 自
启动的功能以便产生出厂设置的默认输出频率,或者可
通过 I
2
C 串行接口在系统中对器件寄存器和 EEPROM
设置进行完全编程。该器件通过 I
2
C 串行接口提供精细
和粗糙的频率裕量控制,因此成为一种数控振荡器
(DCXO)。
您可以更新 PLL 反馈分频器,从而使用 12.5MHz 的
PFD(R 分频器=4,禁用倍频器)以小于 1ppb 的步进
值进行无峰值或毛刺的输出频率调节以符合 xDSL 要
求,或使用 100MHz 的 PFD(R 分频器=1,启用倍频
器)以小于 5.2ppb 的步进值进行此调节以符合广播视
频要求。频率裕量 特性 也有利于进行系统设计验证测
试 (DVT),如标准合规性和系统时序裕量测试。
器器件件信信息息
(1)
器器件件编编号号 封封装装 封封装装尺尺寸寸((标标称称值值))
LMK61E07 QFM (6) 7.00mm x 5.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
引引脚脚分分布布和和简简化化框框图图
2
LMK61E07
ZHCSH74A –DECEMBER 2017–REVISED OCTOBER 2018
www.ti.com.cn
Copyright © 2017–2018, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics - Power Supply ................. 5
6.6 LVPECL Output Characteristics................................ 5
6.7 LVDS Output Characteristics .................................... 5
6.8 HCSL Output Characteristics.................................... 5
6.9 Frequency Tolerance Characteristics ....................... 6
6.10 Frequency Margining Characteristics ..................... 6
6.11 Power-On Reset Characteristics (VDD).................. 6
6.12 I
2
C-Compatible Interface Characteristics (SDA,
SCL)........................................................................... 6
6.13 PSRR Characteristics ............................................. 7
6.14 Other Characteristics .............................................. 7
6.15 PLL Clock Output Jitter Characteristics .................. 7
6.16 Typical 156.25-MHz Output Phase Noise
Characteristics ........................................................... 7
6.17 Typical 161.1328125 MHz Output Phase Noise
Characteristics ........................................................... 8
6.18 Additional Reliability and Qualification.................... 8
6.19 Typical Characteristics............................................ 9
7 Parameter Measurement Information ................ 13
7.1 Device Output Configurations................................. 13
8 Detailed Description............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
8.5 Programming........................................................... 22
8.6 Register Maps......................................................... 26
9 Application and Implementation ........................ 39
9.1 Application Information............................................ 39
9.2 Typical Application .................................................. 39
10 Power Supply Recommendations ..................... 43
11 Layout................................................................... 43
11.1 Layout Guidelines ................................................. 43
11.2 Layout Example .................................................... 44
12 器器件件和和文文档档支支持持 ..................................................... 45
12.1 文档支持 ............................................................... 45
12.2 接收文档更新通知 ................................................. 45
12.3 社区资源................................................................ 45
12.4 商标 ....................................................................... 45
12.5 静电放电警告......................................................... 45
12.6 术语表 ................................................................... 45
13 机机械械、、封封装装和和可可订订购购信信息息....................................... 45
4 修修订订历历史史记记录录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (December 2017) to Revision A Page
• Changed the Loop Filter Structure of PLL graphic .............................................................................................................. 18
• Changed the LMK61E07 Interface and Control Block graphic ............................................................................................ 20
SCL OUTN
VDDSDA
GND OUTP
1 6
2 5
43
3
LMK61E07
www.ti.com.cn
ZHCSH74A –DECEMBER 2017 –REVISED OCTOBER 2018
Copyright © 2017–2018, Texas Instruments Incorporated
5 Pin Configuration and Functions
SIA Package
6-Pin QFM
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
POWER
GND 3 Ground Device Ground.
VDD 6 Power 3.3-V Power Supply.
OUTPUT BLOCK
OUTP,
OUTN
4, 5 Output Differential Output Pair (LVPECL, LVDS, or HCSL).
DIGITAL CONTROL / INTERFACES
SCL 2 LVCMOS I
2
C Serial Clock (open-drain). Requires an external pullup resistor to VDD.
SDA 1 LVCMOS I
2
C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD.
4
LMK61E07
ZHCSH74A –DECEMBER 2017–REVISED OCTOBER 2018
www.ti.com.cn
Copyright © 2017–2018, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
VDD Device supply voltage –0.3 3.6 V
V
IN
Input voltage for logic inputs –0.3 VDD + 0.3 V
V
OUT
Output voltage for clock outputs –0.3 VDD + 0.3 V
T
J
Junction temperature 150 °C
T
STG
Storage temperature –40 125 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101
(2)
±500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Device supply voltage 3.135 3.3 3.465 V
T
A
Ambient temperature –40 25 85 °C
T
J
Junction temperature 115 °C
t
RAMP
VDD power-up ramp time 0.1 100 ms
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal resistance is calculated on a 4-layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψ
JB
(junction-to-board) is used when the main heat flow is from the junction to the GND pad. See Layout Guidelines for more information
on ensuring good system reliability and quality.
6.4 Thermal Information
THERMAL METRIC
(1)
LMK61E07
(2) (3) (4)
UNIT
SIA (QFM)
8 PINS
Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400
R
θJA
Junction-to-ambient thermal resistance 54 44 41.2 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 34 n/a n/a °C/W
R
θJB
Junction-to-board thermal resistance 36.7 n/a n/a °C/W
ψ
JT
Junction-to-top characterization parameter 11.2 16.9 21.9 °C/W
ψ
JB
Junction-to-board characterization parameter 36.7 37.8 38.9 °C/W
R
θJC(bot)
Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
5
LMK61E07
www.ti.com.cn
ZHCSH74A –DECEMBER 2017 –REVISED OCTOBER 2018
Copyright © 2017–2018, Texas Instruments Incorporated
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.
6.5 Electrical Characteristics - Power Supply
(1)
VDD = 3.3 V ± 5%, T
A
= –40°C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Device current consumption LVPECL
(2)
162 208
mA
HCSL 155 196
IDD-PD Device current consumption
when output is disabled
120
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over f
OUT
maximum spec is possible, but output swing may be less than V
OD
minimum spec.
(3) Ensured by characterization.
6.6 LVPECL Output Characteristics
(1)
VDD = 3.3 V ± 5%, T
A
= –40C to 85° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
OUT
Output frequency
(2)
10 1000 MHz
V
OD
Output voltage swing
(V
OH
- V
OL
)
(2)
700 800 1200 mV
V
OUT, DIFF, PP
Differential output peak-to-
peak swing
2 x
|V
OD
|
V
V
OS
Output common-mode voltage VDD –
1.55
V
t
R
/ t
F
Output rise/fall time (20% to
80%)
(3)
120 200 ps
PN-Floor Output phase noise floor
(f
OFFSET
> 10 MHz)
156.25 MHz
–165
dBc/Hz
ODC Output duty cycle
(3)
45% 55%
(1) An output frequency over f
OUT
max spec is possible, but output swing may be less than V
OD
min spec.
(2) Ensured by characterization.
6.7 LVDS Output Characteristics
(1)
VDD = 3.3 V ± 5%, T
A
= –40°C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
OUT
Output Frequency
(1)
10 900 MHz
V
OD
Output Voltage Swing
(V
OH
- V
OL
)
(1)
300 390 480 mV
V
OUT, DIFF, PP
Differential Output Peak-to-
Peak Swing
2 x
|V
OD
|
V
V
OS
Output Common Mode
Voltage
1.2 V
t
R
/ t
F
Output Rise/Fall Time (20% to
80%)
(2)
150 250 ps
PN-Floor Output Phase Noise Floor
(f
OFFSET
> 10 MHz)
156.25 MHz
–162 dBc/Hz
ODC Output Duty Cycle
(2)
45% 55%
R
OUT
Differential Output Impedance 125 Ω
(1) Refer to Parameter Measurement Information for relevant test conditions.
6.8 HCSL Output Characteristics
(1)
VDD = 3.3 V ± 5%, T
A
= –40°C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
OUT
Output frequency 10 400 MHz
V
OH
Output high voltage 600 850 mV
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