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TI-TLC2933A.pdf
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TI-TLC2933A.pdf
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SLES149 − OCTOBER 2005
1
TI.COM
D VCO (Voltage-Controlled Oscillator):
− Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
− Lock Frequency:
30 MHz to 55 MHz (VDD = 3 V +5%,
T
A
= –205C to 755C, x1 Output)
30 MHz to 60 MHz (VDD = 3.3 V +5%,
T
A
= –205C to 755C, x1 Output)
43 MHz to 110 MHz (VDD = 5 V + 5%,
T
A
= –205C to 755C, x1 Output)
− Selectable Output Frequency
D PFD (Phase Frequency Detector):
High Speed, Edge-Triggered Detector
with Internal Charge Pump
D Independent VCO, PFD Power-Down Mode
D Thin Small-Outline Package (14 Terminal)
D CMOS Technology
D Pin Compatible TLC2933IPW
description
The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
BIAS
). The VCO has a 1/2 frequency divider at the output stage.
The high speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability,
the TLC2933A is suitable for use as a high-performance PLL.
AVAILABLE OPTIONS
T
A
PACKAGE
T
A
SMALL OUTLINE (PW)
–20°C to 75°C TLC2933AIPW
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LOGIC V
DD
SELECT
VCO OUT
FIN−A
FIN−B
PFD OUT
LOGIC GND
VCO V
DD
RBIAS
VCO
IN
VCO GND
VCO INHIBI
T
PFD INHIBIT
TEST
14-PIN TSOP (PW PACKAGE)
(TOP VIEW)
Copyright 2005, Texas Instruments Incorporated
SLES149 − OCTOBER 2005
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TI.COM
functional block diagram
4
5
6
9
12
13
10
2
3
FIN−A
FIN−B
PFD INHIBIT
VCO IN
BIAS
VCO INHIBIT
SELECT
VCO OUT
PFD OUT
Phase
Frequency
Detector
Voltage
Controlled
Oscillator
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
LOGIC VDD 1 Power supply for the internal logic. This power supply should be separated from VCO V
DD
to reduce
cross-coupling between supplies.
SELECT 2 I VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when
low. The output frequency is ×1.
VCO OUT 3 O VCO output. When the VCO INHIBIT is high, VCO output is low.
FIN−A 4 I Input reference frequency f
(REF
IN)
is applied to FIN−A.
FIN−B 5 I Input for VCO external counter output frequency f
(FIN−B)
. FIN−B is nominally provided from the
external counter.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
LOGIC GND 7 GND for the internal logic.
TEST 8 Connect to GND.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state.
VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO output is low.
VCO GND 11 GND for VCO.
VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control
VCO oscillation frequency.
RBIAS 13 I Bias supply. An external resistor (R
BIAS
) between VCO V
DD
and R
BIAS
supplies bias for adjusting the
oscillation frequency range.
VCO V
DD
14 Power supply for VCO. This power supply should be separated from LOGIC V
DD
to reduce
cross-coupling between supplies.
SLES149 − OCTOBER 2005
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TI.COM
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external register (R
BIAS
) connected between the VCO V
DD
and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock
frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
Bias Resistor (R
BIAS
)
VCO Oscillation Frequency Range
1/2 V
DD
VCO Control Voltage (VCO IN)
VCO Oscillation Frequency − f
OSC
Figure 1. Oscillation Frequency
VCO output frequency 1/2 divider
The TLC2933A SELECT terminal sets the f
OSC
VCO output frequency as shown in Table 1. The 1/2 f
OSC
output
should be used for minimum VCO output jitter.
Table 1.
VCO Output 1/2 Divider Function
SELLECT VCO OUTPUT
Low f
OSC
High 1/2 f
OSC
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power−down mode as shown in Table 2.
Table 2.
VCO Inhibit Function
VCO INHIBIT VCO OSCILLATOR VCO OUT I
DD(VCO)
Low Active Active Normal
High Stopped Low level Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the
reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock
recovery PLL system, other types of phase detectors should be used.
SLES149 − OCTOBER 2005
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TI.COM
FIN−A
FIN−B
PFD OUT
V
OH
HI-Z
V
OL
Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT DETECTION PFD OUT I
DD(PFD)
Low Active Active Normal
High Stopped Hi−Z Power Down
VCO block schematic
PFD block schematic
FIN−A
FIN−B
PFD INHIBIT
PFD OUT
V
DD
Charge Pump
Detector
SLES149 − OCTOBER 2005
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TI.COM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage (each supply), V
DD
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (each input), V
IN
(see Note 1) −0.5 V to V
DD
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (each input), I
IN
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (each output), I
O
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25_C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
recommended operating conditions
PARAMETERS MIN TYP MAX UNIT
V
DD
= 3 V 2.85 3 3.15
Supply voltage (each supply, see Note 3)
V
DD
= 3.3 V 3.135 3.3 3.465
V
Supply voltage (each supply, see Note 3)
V
DD
= 5 V 4.75 5 5.25
V
Input voltage, (inputs except VCO IN) 0 V
DD
V
Output current, (each output) 0 ±2 mA
VCO control voltage at VCO IN 0.9 V
DD
V
V
DD
= 3 V 30 55
Lock frequency
V
DD
= 3.3 V 30 60
MHz
Lock frequency
V
DD
= 5 V 43 110
MHz
V
DD
= 3 V 2.2 5.1
Bias resisitor
V
DD
= 3.3 V 2.2 5.1
kΩ
Bias resisitor
V
DD
= 5 V 2.2 5.1
kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC V
DD
) and the VCO supply terminal (VCO V
DD
) should be at the same voltage
and separated from each other.
electrical characteristics, V
DD
= 3 V, T
A
= 25°C (unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High level output voltage I
OH
= –2 mA 2.4 V
V
OL
Low level output voltage I
OL
= 2 mA 0.3 V
V
TH
Input threshold voltage at select, VCO inhibit 0.9 1.5 2.1 V
I
I
Input current at Select, VCO inhibit V
I
= V
DD
or GND ±1 µA
Z
I(VCO
IN)
VCO IN input impedance VCO IN = 1/2 V
DD
10 MΩ
I
DD(INH)
VCO supply current (inhibit) See Note 4 0.41 1 µA
I
DD(VCO)
VCO supply current See Note 5 11.7 23 mA
NOTES: 4. Current into VCO V
DD
, when VCO INHIBIT = high, PFD is inhibited.
5. Current into VCO V
DD
, when VCO IN = 1/2 V
DD
, R
BIAS
= 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and
PFD INHIBIT = GND.
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