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TI-TLC5510A.pdf
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TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Analog Input Range
– TLC5510 ...2 V Full Scale
– TLC5510A ...4 V Full Scale
D
8-Bit Resolution
D
Integral Linearity Error
±0.75 LSB Max (25°C)
±1 LSB Max (–20°C to 75°C)
D
Differential Linearity Error
±0.5 LSB Max (25°C)
±0.75 LSB Max (–20°C to 75°C)
D
Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Max
D
5-V Single-Supply Operation
D
Low Power Consumption
TLC5510 . . . 127.5 mW Typ
TLC5510A . . . 150 mW Typ
(includes reference resistor dissipation)
D
TLC5510 is Interchangeable With Sony
CXD1175
applications
D
Digital TV
D
Medical Imaging
D
Video Conferencing
D
High-Speed Data Conversion
D
QAM Demodulators
description
The TLC5510 and TLC5510A are CMOS, 8-bit, 20
MSPS analog-to-digital converters (ADCs) that
utilize a semiflash architecture. The TLC5510 and
TLC5510A operate with a single 5-V supply and
typically consume only 130 mW of power.
Included is an internal sample-and-hold circuit,
parallel outputs with high-impedance mode, and
internal reference resistors.
The semiflash architecture reduces power
consumption and die size compared to flash
converters. By implementing the conversion in a
2-step process, the number of comparators is
significantly reduced. The latency of the data
output valid is 2.5 clocks.
The TLC5510 uses the three internal reference
resistors to create a standard, 2-V, full-scale
conversion range using V
DDA
. Only external jumpers are required to implement this option and eliminates the
need for external reference resistors. The TLC5510A uses only the center internal resistor section with an
externally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C
and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include
a differential gain of 1% and differential phase of 0.7 degrees.
The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C.
AVAILABLE OPTIONS
PACKAGE
MAXIMUM FULL SCALE
T
A
TSSOP (PW)
SOP (NS)
(TAPE AND REEL ONLY)
MAXIMUM
FULL
-
SCALE
INPUT VOLTAGE
20°Cto75°C
TLC5510IPW TLC5510INSLE 2 V
–
20°C
to
75°C
– TLC5510AINSLE 4 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1994 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
DGND
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
V
DDD
CLK
DGND
REFB
REFBS
AGND
AGND
ANALOG IN
V
DDA
REFT
REFTS
V
DDA
V
DDA
V
DDD
PW OR NS PACKAGE
†
(TOP VIEW)
†
Available in tape and reel only and ordered
as the shown in the Available Options table
below.
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
Lower Data
Latch
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
Upper Sampling
Comparators
(4-Bit)
Upper Encoder
(4-Bit)
Upper Data
Latch
Clock
Generator
OE
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
CLK
REFB
REFT
REFBS
AGND
AGND
ANALOG IN
V
DDA
REFTS
270 Ω
NOM
80 Ω
NOM
320 Ω
NOM
Resistor
Reference
Divider
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
V
DDA
AGND
ANALOG IN
EQUIVALENT OF EACH DIGITAL INPUT
V
DDD
DGND
OE, CLK
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDD
DGND
D1–D8
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 20, 21 Analog ground
ANALOG IN 19 I Analog input
CLK 12 I Clock input
DGND 2, 24 Digital ground
D1–D8 3–10 O Digital data out. D1 = LSB, D8 = MSB
OE 1 I Output enable. When OE = low, data is enabled. When OE = high, D1–D8 is in high-impedance state.
V
DDA
14, 15, 18 Analog supply voltage
V
DDD
11, 13 Digital supply voltage
REFB 23 I Reference voltage in bottom
REFBS 22 Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to
ground.
REFT 17 I Reference voltage in top
REFTS 16 Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to
V
DDA
.
absolute maximum ratings
†
Supply voltage, V
DDA
, V
DDD
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, V
REFT
, V
REFB
AGND to V
DDA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, V
I(ANLG)
AGND to V
DDA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, V
I(DGTL)
DGND to V
DDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, V
O(DGTL)
DGND to V
DDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
V
DDA
–AGND 4.75 5 5.25
V
Supply voltage
V
DDD
–AGND 4.75 5 5.25
V
AGND–DGND –100 0 100 mV
Reference input voltage (top), V
ref(T)
‡
TLC5510A V
REFB
+2 4 V
Reference input voltage (bottom), V
ref(B)
‡
TLC5510A 0 V
REFT
–4 V
Analog input voltage range, V
I(ANLG)
V
REFB
V
REFT
V
High-level input voltage, V
IH
4 V
Low-level input voltage, V
IL
1 V
Pulse duration, clock high, t
w(H)
(see Figure 1) 25 ns
Pulse duration, clock low, t
w(L)
(see Figure 1) 25 ns
‡
The reference voltage levels for the TLC5510 are derived through an internal resistor divider between V
DDA
and ground and therefore are not
derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the
reference voltage is externally applied across the center divider resistor.
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at V
DD
= 5 V, V
REFT
= 2.5 V, V
REFB
= 0.5 V, f
(CLK)
= 20 MHz, T
A
= 25°C (unless
otherwise noted)
digital I/O
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
I
IH
High-level input current V
DD
= MAX, V
IH
= V
DD
5
µA
I
IL
Low-level input current V
DD
= MAX, V
IL
= 0 5
µ
A
I
OH
High-level output current OE = GND, V
DD
= MIN, V
OH
= V
DD
–0.5 V –1.5
mA
I
OL
Low-level output current OE = GND, V
DD
= MIN, V
OL
= 0.4 V 2.5
mA
I
OZH
High-level high-impedance-state
output leakage current
OE = V
DD
, V
DD
= MAX V
OH
= V
DD
16
µA
I
OZL
Low-level high-impedance-state
output leakage current
OE = V
DD
, V
DD
= MIN V
OL
= 0 16
µ
A
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
power
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
I
DD
Supply current
f
(CLK)
= 20 MHz, National Television System Committee (NTSC)
ramp wave input, reference resistor dissipation is separate
18 27 mA
I
f
Reference voltage current
TLC5510 V
ref
= REFT – REFB = 2 V 5.2 7.5 10.5 mA
I
ref
Reference
voltage
current
TLC5510A V
ref
= REFT – REFB = 4 V 10.4 15 21 mA
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
static performance
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
Self-bias (1), at REFB
Short REFB to REFBS
Short REFT to REFTS
0.57 0.61 0.65
Self-bias (2), REFT – REFB
Short
REFB
to
REFBS
,
Short
REFT
to
REFTS
1.9 2.02 2.15
V
Self-bias (3), at REFT Short REFB to AGND, Short REFT to REFTS 2.18 2.29 2.4
R
ref
Reference voltage resistor Between REFT and REFB 190 270 350 Ω
C
i
Analog input capacitance V
I(ANLG)
= 1.5 V + 0.07 V
rms
16 pF
TLC5510
f
(CLK)
= 20 MHz,
T
A
= 25°C ±0.4 ±0.75
Integral nonlinearity (INL)
TLC5510
(CLK)
,
V
I
= 0.5 V to 2.5 V
T
A
= –20°C to 75°C ±1
Integral
nonlinearity
(INL)
TLC5510A
f
(CLK)
= 20 MHz,
T
A
= 25°C ±0.4 ±0.75
TLC5510A
(CLK)
,
V
I
= 0 to 4 V
T
A
= –20°C to 75°C ±1
LSB
TLC5510
f
(CLK)
= 20 MHz,
T
A
= 25°C ±0.3 ±0.5
LSB
Differential nonlinearity (DNL)
TLC5510
(CLK)
,
V
I
= 0.5 V to 2.5 V
T
A
= –20°C to 75°C ±0.75
Differential
nonlinearity
(DNL)
TLC5510A
f
(CLK)
= 20 MHz,
T
A
= 25°C ±0.3 ±0.5
TLC5510A
(CLK)
,
V
I
= 0 to 4 V
T
A
= –20°C to 75°C ±0.75
E
ZS
Zero scale error
TLC5510 V
ref
= REFT – REFB = 2 V –18 –43 –68 mV
E
ZS
Zero
-
scale
error
TLC5510A V
ref
= REFT – REFB = 4 V –36 –86 –136 mV
E
FS
Full-scale error
TLC5510 V
ref
= REFT – REFB = 2 V –20 0 20 mV
E
FS
Full
-
scale
error
TLC5510A V
ref
= REFT – REFB = 4 V –40 0 40 mV
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at V
DD
= 5 V, V
REFT
= 2.5 V, V
REFB
= 0.5 V, f
(CLK)
= 20 MHz, T
A
= 25°C (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
Maximum conversion rate
TLC5510
f
I
= 1 kHz ram
p
V
I(ANLG)
= 0.5 V – 2.5 V 20 MSPS
f
conv
Maximum
conversion
rate
TLC5510A
f
I
=
1
-
kHz
ramp
V
I(ANLG)
= 0 V – 4 V 20 MSPS
BW Analog input bandwidth At – 1 dB 14 MHz
t
d(D)
Digital output delay time C
L
≤ 10 pF (see Note 1 and Figure 1) 18 30 ns
Differential gain
NTSC 40 Institute of Radio En
g
ineers (IRE)
1%
Differential phase
g()
modulation wave, f
conv
= 14.3 MSPS
0.7 degrees
t
AJ
Aperture jitter time 30 ps
t
d(s)
Sampling delay time 4 ns
t
en
Enable time, OE↓ to valid data C
L
= 10 pF 5 ns
t
dis
Disable time, OE↑ to high impedance C
L
= 10 pF 7 ns
In
p
ut tone = 1 MHz
T
A
= 25°C 45
Input
tone
=
1
MHz
Full range 43
In
p
ut tone = 3 MHz
T
A
= 25°C 45
S
p
urious free dynamic range (SFDR)
Input
tone
=
3
MHz
Full range 46
dB
Spurious
free
dynamic
range
(SFDR)
In
p
ut tone = 6 MHz
T
A
= 25°C 43
dB
Input
tone
=
6
MHz
Full range 42
In
p
ut tone = 10 MHz
T
A
= 25°C 39
Input
tone
=
10
MHz
Full range 39
SNR
Signal to noise ratio
T
A
= 25°C 46
dB
SNR
Signal
-
to
-
noise
ratio
Full range 44
dB
NOTE 1: C
L
includes probe and jig capacitance.
N
N+1
N+2
N+3
N+4
N–3N–2N–1NN+1
t
d(D)
CLK (clock)
ANALOG IN
(input signal)
D1–D8
(output data)
t
w(H)
t
w(L)
t
d(s)
Figure 1. I/O Timing Diagram
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