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FEATURES

• Precision Fault Threshold

• Programmable:

Average Power Limiting, Linear

Current Control, Overcurrent Limit

and Fault Time

• Fault Output Indication Signal

• Automatic Retry Mode or Latched

Operation Mode

• Shutdown Control

• Undervoltage Lockout

• 250µs Glitch Filter on the SDFLTCH

• 8-Pin DIL and SOIC

Latchable Negative Floating Hot Swap Power Manager

BLOCK DIAGRAM

UCC1921

UCC2921

UCC3921

UDG-99052

DESCRIPTION

The UCC3921 family of negative floating hot swap power managers pro-

vides complete power management, hot swap, and fault handling capa-

bility. The IC is referenced to the negative input voltage and is powered

through an external resistor connected to ground, which is essentially a

current drive as opposed to the traditional voltage drive. The onboard

10V shunt regulator protects the IC from excess voltage and serves as a

reference for programming the maximum allowable output sourcing cur-

rent during a fault. All control and housekeeping functions are integrated

and externally programmable. These include the fault current level, maxi-

mum output sourcing current, maximum fault time, selection of Retry or

Latched mode, soft start time, and average power limiting. In the event of

a constant fault, the internal timer will limit the on time from less than

0.1% to a maximum of 3% duty cycle. The duty cycle modulation de-

pends on the current into PL, which is a function of the voltage across

the FET, thus limiting average power dissipation in the FET. The fault

level is fixed at 50mV across the current sense amplifier to minimize total

(continued)

UCC1921

UCC2921

UCC3921

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, T

= 0°C to 70°C for the UCC3921 and –40°C to 85°C

for the UCC2921, and –55°C to 125°C for the UCC1921; I

VDD

= 2mA, C

= 1nF (the minimum allowable value), there is no

resistor connected between the SDFLTCH and VSS pins. T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VDD Section

IDD 12mA

Regulator Voltage I

SOURCE

= 2mA 9 9.5 10.0 V

SOURCE

= 10mA 9.15 9.6 10.15 V

UVLO Off Voltage 67 8V

Fault Timing Section

Overcurrent Threshold T

= 25°C 47.5 50 53.5 mV

Over Operating Temperature 46 50 53.5 mV

Overcurrent Input Bias 50 500 nA

CT Charge Current V

= 1V, I

= 0 –50 –36 –22 µA

Overload Condition, V

SENSE

-V

IMAX

= 300mV –1.7 –1.2 –0.7 mA

CT Discharge Current V

= 1V, I

= 0 0.6 1 1.5 µA

CT Fault Threshold 2.2 2.45 2.6 V

CT Reset Threshold 0.41 0.49 0.57 V

Output Duty Cycle Fault Condition, I

= 0 1.7 2.7 3.7 %

CONNECTION DIAGRAM

DIL-8 , SOIC-8 (Top View)

NorJ,DPackages

ABSOLUTE MAXIMUM RATINGS

IVDD..........................................50mA

SDFLTCH Current ..............................10mA

PL Current ....................................10mA

IMAX Input Voltage ..............................VDD

Storage Temperature ...................−65°C to +150°C

Junction Temperature...................–55°C to +150°C

Lead Temperature (Soldering, 10 sec.) .............+300°C

All voltages are with respect to V

(the most negative voltage).

Currents are positive into, negative out of the specified terminal.

Consult Packaging Section of Databook for thermal limitations and

considerations of packages.

dropout. The fault current level is set with an external

current sense resistor, while the maximum allowable

sourcing current is programmed with a voltage divider

from VDD to generate a fixed voltage on IMAX. The cur-

rent level, when the output acts as a current source, is

equal to V

IMAX/RSENSE. If desired, a controlled current

start up can be programmed with a capacitor on IMAX.

When the output current is below the fault level, the out-

put device is switched on. When the output current ex-

ceeds the fault level, but is less than the maximum

sourcing level programmed by IMAX, the output remains

switched on, and the fault timer starts charging C

T. Once

T charges to 2.5V, the output device is turned off and

performs a retry some time later (provided that the se-

lected mode of operation is Automatic Retry Mode).

When the output current reaches the maximum sourcing

current level, the output acts as a current source, limiting

the output current to the set value defined by IMAX.

Other features of the UCC3921 include undervoltage

lockout, 8-pin Small Outline (SOIC) and Dual-In-Line

(DIL) packages, and a Latched Operation Mode option,

in which the output is latched off once C

T charges to

2.5V and stays off until either SDFLTCH is toggled (for

greater than 1ms) or the IC is powered down and then

back up.

DESCRIPTION (continued)

UCC1921

UCC2921

UCC3921

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, T

= 0°C to 70°C for the UCC3921 and –40°C to 85°C

for the UCC2921, and –55°C to 125°C for the UCC1921; I

VDD

= 2mA, C

= 1nF (the minimum allowable value), there is no

resistor connected between the SDFLTCH and VSS pins. T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Section

Output High Voltage I

OUT

= 0mA 8.5 10 V

OUT

= –1mA 6 8 V

Output Low Voltage I

OUT

= 0mA, V

SENSE

–V

IMAX

= 100mV 0 10 mV

OUT

= 2mA, V

SENSE

–V

IMAX

= 100mV 200 600 mV

Linear Amplifier Section

Sense Control Voltage V

IMAX

= 100mV 85 100 115 mV

IMAX

= 400mV 370 400 430 mV

Input Bias 50 500 nA

Power Limiting Section

SENSE Regulator Voltage I

=64µA 4.35 4.85 5.35 V

Duty Cycle Control I

=64µA 0.6 1.2 1.7 %

= 1mA 0.045 0.1 0.17 %

Overload Section

Delay to Output Note 1 300 500 ns

Output Sink Current V

SENSE

–V

IMAX

= 300mV 40 100 mA

Threshold Relative to IMAX 140 200 260 mV

Shutdown/Fault/Latch Section

Shutdown Threshold 3 5 VDD+1 V

Input Current V

SDFLTCH

= 5V 50 110 250 µA

Filter Delay Time (Delay to Output) 250 500 1000 µs

Fault Output High 6 9.5 V

SDFLTCH

= –100µA 5 8.5 V

Fault Output Low 010mV

Output Duty Cycle Fault Condition, I

= 0 1.7 2.7 3.7 %

SDFLTCH

= –100µA, Fault Condition, I

=0 0 %

Note 1: Guaranteed by design. Not 100% tested in production.

PIN DESCRIPTIONS

CT: A capacitor is connected to this pin in order to set

the fault time. The fault time must be longer than the time

to charge external load capacitance. The fault time is

defined as:

FAULT

•

where ICH =36µA+IPL, and IPL is the current into the

power limit pin. Once the maximum fault time is reached

the output will shutdown for a time given by:

SD T

=• •

210

IMAX: This pin programs the maximum allowable

sourcing current. Since VDD is a regulated voltage, a

voltage divider can be derived from VDD to generate the

program level for IMAX. The current level at which the

output appears as a current source is equal to the

voltage on IMAX over the current sense resistor. If

desired, a controlled current start up can be programmed

with a capacitor on IMAX, and a programmed start delay

can be achieved by driving the shutdown with an open

collector/drain device into an RC network.

OUT: This pin provides gate output drive to the MOSFET

pass element.

PL: This feature ensures that the average MOSFET

power dissipation is controlled. A resistor is connected

from this pin to the drain of the NMOS pass element.

When the voltage across the NMOS exceeds 5V, current

will flow into the PL pin which adds to the fault timer

charge current, reducing the duty cycle from the 3%

level. When I

>>36µA, then the average MOSFET

power dissipation is given by:

P avg IMAX R

MOSFET PL

=•••

−

110

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