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TI-SN75LBC175.pdf
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SLLS171G − OCTOBER 1993 − REVISED MARCH2009
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Meets or Exceeds the EIA Standards
RS-422-A, RS-423-A, RS-485, and CCITT
Recommendation V.11
D Designed to Operate With Pulse Durations
as Short as 20 ns
D Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D Input Sensitivity . . . ±200 mV
D Low-Power Consumption...20 mA Max
D Open-Circuit Fail-Safe Design
D Common-Mode Input Voltage Range of
−7 V to 12 V
D Pin Compatible With SN75175 and LTC489
description
The SN65LBC175 and SN75LBC175 are monolithic, quadruple, differential line receivers with 3-state outputs
designed to meet the requirements of the EIA standards RS-422-A, RS-423-A, RS-485, and CCITT
Recommendation V.11. The devices are optimized for balanced multipoint bus transmission at data rates up
to and exceeding 10 million bits per second. The receivers are enabled in pairs, with an active-high enable input.
Each differential receiver input features high impedance, hysteresis for increased noise immunity, and
sensitivity of ±200 mV over a common-mode input voltage range of 12 V to −7 V. The fail-safe design ensures
that when the inputs are open-circuited, the outputs are always high. Both devices are designed using the TI
proprietary LinBiCMOStechnology allowing low power consumption, high switching speeds, and robustness.
These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line
drivers. The SN65LBC175 is available in the 16-pin DIP (N), small-outline package (D), and the wide
small-outline package (DW). The SN75LBC175 is available in the 16-pin DIP (N) and the small-outline package
(D).
The SN65LBC175 is characterized over the industrial temperature range of −40°C to 85°C. The SN75LBC175
is characterized for operation over the commercial temperature range of 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGE
TEMPERATURE RANGE
PACKAGE
0°C to 70°C −40°C to 85°C
SOIC SN75LBC175D SN65LBC175D
Wide SOIC SN65LBC175DW
PDIP SN75LBC175N SN65LBC175N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2009 Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
V
CC
4B
4A
4Y
3,4EN
3Y
3A
3B
D, DW, OR N PACKAGE
(TOP VIEW)
LinBiCMOS is a trademark of Texas Instruments.
SLLS171G − OCTOBER 1993 − REVISED MARCH2009
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
2B
2A
1B
1A
1,2EN
2Y
1Y
5
3
7
6
1
2
4
EN
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
4B
4A
3B
3A
3,4EN
4Y
3Y
13
11
15
14
9
10
12
EN
logic diagram (positive logic)
2Y
1Y
5
3
7
6
1
2
4
2B
2A
1B
1A
1,2EN
4Y
3Y
13
11
15
14
9
10
12
4B
4A
3B
3A
3,4EN
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A−B
ENABLE
OUTPUT
Y
V
ID
≥ 0.2 V H H
−0.2 V < V
ID
< 0.2 V H ?
V
ID
≤ −0.2 V H L
X L Z
Open circuit H H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
V
CC
Y Output
EQUIVALENT OF A AND B INPUTS
12 kΩ
3 kΩ
18 kΩ
1 kΩ
V
CC
Input
100 kΩ
(A Only)
100 kΩ
(B Only)
Input
V
CC
TYPICAL OF EN INPUT
Outpu
t
Receiver
SLLS171G − OCTOBER 1993 − REVISED MARCH2009
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(A or B inputs) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
ID
(see Note 2) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at Y, 1/2EN, 3/4EN −0.3 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN65LBC175 −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75LBC175 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Discharge (ESD): Human Body Model (HBM) 1 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Model (MM) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged Device Model (CDM) 1.5 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE T
A
= 25°C
T
A
= 70°C
POWER RATING
T
A
= 85°C
POWER RATING
D 1100 mW 8.7 mW/°C 709 mW 578 mW
DW 1200 mW 9.6 mW/°C 770 mW 625 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.75 5 5.25 V
Common-mode input voltage, V
IC
−7 12 V
Differential input voltage, V
ID
± 6 V
High-level input voltage, V
IH
EN inputs
2 V
Low-level input voltage, V
IL
EN inputs
0.8 V
High-level output current, I
OH
−8 mA
Low-level output current, I
OL
8 mA
Operating free-air temperature, T
A
SN65LBC175 −40 85
°C
Operating free-air temperature, T
A
SN75LBC175 0 70
°C
SLLS171G − OCTOBER 1993 − REVISED MARCH2009
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT+
Positive-going input threshold voltage I
O
= −8 mA 0.2 V
V
IT−
Negative-going input threshold voltage I
O
= 8 mA −0.2 V
V
hys
Hysteresis voltage (V
IT+
− V
IT−
) 45 mV
V
IK
Enable input clamp voltage I
I
= −18 mA −0.9 −1.5 V
V
OH
High-level output voltage V
ID
= 200 mV, I
OH
= −8 mA 3.5 4.5 V
V
OL
Low-level output voltage V
ID
= −200 mV, I
OL
= 8 mA 0.3 0.5 V
I
OZ
High-impedance-state output current V
O
= 0 V to V
CC
± 20 µA
V
IH
= 12 V, V
CC
= 5 V, Other inputs at 0 V 0.7 1
I
I
Bus input current
A or B inputs
V
IH
= 12 V, V
CC
= 0 V, Other inputs at 0 V 0.8 1
mA
I
I
Bus input current A or B inputs
V
IH
= −7 V, V
CC
= 5 V, Other inputs at 0 V −0.5 −0.8
mA
V
IH
= −7 V, V
CC
= 0 V, Other inputs at 0 V −0.4 −0.8
I
IH
High-level enable input current V
IH
= 5 V ± 20 µA
I
IL
Low-level enable input current V
IL
= 0 V −20 µA
I
OS
Short-circuit output current V
O
= 0 −80 −120 mA
I
CC
Supply current
Outputs enabled, I
O
= 0, V
ID
= 5 V 11 20
mA
I
CC
Supply current
Outputs disabled 0.9 1.4
mA
†
All typical values are at V
CC
= 5 V and T
A
= 25°C.
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
t
PHL
Propagation delay time, high- to low-level output
V
ID
= −1.5 V to 1.5 V,
11 22 30 ns
t
PLH
Propagation delay time, low- to high-level output
V
ID
= −1.5 V to 1.5 V,
See Figure 1
11 22 30 ns
t
PZH
Output enable time to high level See Figure 2 17 30 ns
t
PZL
Output enable time to low level See Figure 3 18 30 ns
t
PHZ
Output disable time from high level See Figure 2 30 40 ns
t
PLZ
Output disable time from low level See Figure 3 23 30 ns
t
sk(p)
Pulse skew (|t
PHL
− t
PLH
|) See Figure 2 4 6 ns
t
t
Transition time See Figure 1 3 10 ns
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