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DRA829 Jacinto™ 处理器

器件版本 1.0 和 1.1

1 特性

处理器内核：

• 双核 64 位 Arm

Cortex

-A72 微处理器子系统，性

能高达 2.0GHz

– 每个双核 Arm

Cortex

-A72 集群具有 1MB L2

共享缓存

– 每个 Cortex

-A72 内核具有 32KB L1 数据缓存

和 48KB L1 指令缓存

• 六个 Arm

Cortex

-R5F MCU，性能高达 1.0GHz

– 16K 指令缓存，16K 数据缓存，64K L2 TCM

– 隔离 MCU 子系统中有两个 Arm

Cortex

-R5F

MCU

– 通用计算分区中有四个 Arm

Cortex

-R5F

MCU

• 深度学习矩阵乘法加速器 (MMA)，性能高达

8TOPS (8b)（频率为 1.0GHz）

• C7x 浮点矢量 DSP，性能高达 1.0GHz、

80GFLOPS、256GOPS

• 两个 C66x 浮点 DSP，性能高达 1.35GHz、

40GFLOPS、160GOPS

• 3D GPU PowerVR

Rogue 8XE GE8430，性能高

达 750MHz、96GFLOPS、6Gpix/s

存储器子系统：

• 高达 8MB 的片上 L3 RAM（具有 ECC 和一致性）

– ECC 错误保护

– 共享一致性缓存

– 支持内部 DMA 引擎

• 外部存储器接口 (EMIF) 模块（具有 ECC）

– 支持 LPDDR4 存储器类型

– 支持高达 4266MT/s 的速度

– 具有内联 ECC 的 32 位数据总线，数据速率高

达 14.9GB/s

• 通用存储器控制器 (GPMC)

• 主域中的 512KB 片上 SRAM，受 ECC 保护

显示子系统：

• 1 个 eDP/DP 接口，具有多显示器支持 (MST)

– HDCP1.4/HDCP2.2 高带宽数字内容保护

• 1 个 DSI TX（高达 2.5K）

• 多达 2 个 DPI

视频加速：

• 超高清视频，1（3840 × 2160p，60fps）或 2

（3840 × 2160p，30fps）H.264/H.265

解码

• 全高清视频，4（1920 × 1080p，60fps）或 8

（1920 × 1080p，30fps）H.264/H.265

解码

• 全高清视频，1（1920 × 1080p，60fps）或高达 3

（1920 × 1080p，30fps）H.264 编码

功能安全：

• 以符合功能安全标准为目标（在部分器件型号上）

– 专为功能安全应用开发

– 文档有助于使 ISO 26262 功能安全系统设计满

足 ASIL-D/SIL-3 要求

– 系统功能符合 ASIL-D/SIL-3 要求

– 对于 MCU 域，硬件完整性符合 ASIL-D/SIL-3

要求

– 对于主域，硬件完整性符合 ASIL-B/SIL-2 要求

– 安全相关认证

• 计划通过的 ISO 26262 认证

• 符合 AEC-Q100 标准（以 Q1 结尾的器件型号）

• 器件安全（在部分器件型号上）：

• 安全引导，提供安全运行时支持

• 客户可编程的根密钥，级别高达 RSA-4K 或

ECC-512

• 嵌入式硬件安全模块

• 加密硬件加速器 – 带 ECC 的 PKA、AES、SHA、

RNG、DES 和 3DES

高速串行接口：

• 2 个 CSI2.0 4L RX 和 1 个 CSI2.0 4L TX

• 集成以太网交换机支持

（总共 8 个外部端口）

– 多达 8 个 2.5Gb SGMII

– 多达 8 个 RMII (10/100) 或 RGMII

(10/100/1000)

– 多达 2 个 QSGMII

• 最多四个 PCI-Express

(PCIe) 第 3 代控制器

– 第 1 代 (2.5GT/s)、第 2 代 (5.0GT/s) 和第 3 代

(8.0GT/s) 运行，具有自动协商功能

– 每个控制器多达 2 个通道

• 2 个 USB 3.0 双重角色器件 (DRD) 子系统

– 2 个增强型 SuperSpeed 第 1 代端口

– 每个端口都支持 Type-C 开关

– 每个端口均可独立配置为 USB 主机、USB 外设

或 USB DRD

汽车接口：

• 16 个模块化控制器局域网 (MCAN) 模块，具有完整

的 CAN-FD 支持

音频接口：

• 12 个多通道音频串行端口 (MCASP) 模块

闪存接口：

DRA829J, DRA829V

ZHCSN40J – FEBRUARY 2019 – REVISED AUGUST 2021

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SPRSP35

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

3.1 功能模块图.................................................................. 3

4 Revision History.............................................................. 4

5 Device Comparison......................................................... 7

5.1 Related Products........................................................ 9

6 Terminal Configuration and Functions........................10

6.1 Pin Diagram.............................................................. 10

6.2 Pin Attributes.............................................................11

6.3 Signal Descriptions................................................... 79

6.4 Pin Multiplexing.......................................................135

6.5 Connections for Unused Pins................................. 150

7 Specifications.............................................................. 153

7.1 Absolute Maximum Ratings.................................... 153

7.2 ESD Ratings........................................................... 156

7.3 Power-On-Hour (POH) Limits................................. 156

7.4 Recommended Operating Conditions.....................156

7.5 Operating Performance Points................................159

7.6 Power Consumption Summary............................... 159

7.7 Electrical Characteristics.........................................160

7.8 VPP Specifications for One-Time Programmable

(OTP) eFuses............................................................167

7.9 Thermal Resistance Characteristics....................... 169

7.10 Timing and Switching Characteristics................... 170

8 Detailed Description....................................................288

8.1 Overview................................................................. 288

8.2 Processor Subsystems........................................... 289

8.3 Accelerators and Coprocessors..............................290

8.4 Other Subsystems.................................................. 291

9 Applications and Implementation.............................. 300

9.1 Power Supply Mapping........................................... 300

9.2 Device Connection and Layout Fundamentals....... 303

9.3 Peripheral- and Interface-Specific Design

Information................................................................ 305

10 Device and Documentation Support........................310

10.1 Device Nomenclature............................................310

10.2 Tools and Software............................................... 312

10.3 Documentation Support........................................ 313

10.4 支持资源................................................................313

10.5 Trademarks........................................................... 313

10.6 Electrostatic Discharge Caution............................313

10.7 术语表................................................................... 313

11 Mechanical, Packaging, and Orderable

Information.................................................................. 314

11.1 Packaging Information.......................................... 314

4 Revision History

Changes from July 22, 2021 to August 27, 2021 (from Revision I (July 2021) to Revision J

(August 2021)) Page

• 通篇：删除了引用的“DMIPS”.........................................................................................................................1

• (Device Comparison): Deleted "MCU Island with Lockstep Arm Cortex-R5Fs" row, as info in Lockstep and

Safety Targeted rows. ........................................................................................................................................7

• (Pin Attributes): Updated Buffer Type for MCU_PORz and PORz to FS Reset................................................11

• Updated USB0/1_RCALIB footnote to specify the pin must be connected to VSS through an external resistor,

even when the pin is unused.......................................................................................................................... 103

• Updated REXT pin note to show it should always be connected through an external resistor to VSS, even

when unused.................................................................................................................................................. 103

• Added clarification notes to MMC1_SDCD and MMC2_SDCD signals about pulled down requirement....... 109

• Updated CSI0/1_RXRCALIB footnote to specify the pin must be connected to VSS through an external

resistor, even when the pin is unused.............................................................................................................125

• Updated DSI_TXRCALIB footnote to specify the pin must be connected to VSS through an external resistor,

even when the pin is unused.......................................................................................................................... 126

• Showed SERDES[4:0]_REXT balls should be connected to VSS if unused in Connections for Unused Pins.....

150

• Showed VMON balls should be connected to PWR if unused in Connections for Unused Pins. Also added

note specifying MMC1_SDCD and MMC2_SDCD should be pulled down to function properly ....................150

• Showed CSI[1:0]_RXRCALIB, DSI_TXRCALIB, USB[1:0]_RCALIB pins should be connected to VSS is

unused in Connections for Unused Pins ........................................................................................................150

• Added FS Reset Electrical Characteristics table............................................................................................ 160

• (SERDES Electrical Characteristics): Added SERDES REFCLK electrical characteristics table. The limits are

only applicable when internal termination is enabled..................................................................................... 166

• (GPMC and NOR Flash — Sync Burst Read — 4x16–bit): Updated figure for GPMC_WAIT[j] signal (F21,

F22)................................................................................................................................................................ 227

DRA829J, DRA829V

ZHCSN40J – FEBRUARY 2019 – REVISED AUGUST 2021

www.ti.com.cn

4 Submit Document Feedback

Product Folder Links: DRA829J DRA829V

• (GPMC and Multiplexed NOR Flash — Sync Burst Write): Updated figure for GPMC_WAIT[j] signal (F21,

F22)................................................................................................................................................................ 227

• (McSPI): Updated output load limit for SPI_CLK............................................................................................ 258

• (Timing and Switching Characteristics): Updated MMC1, MMC2 SDR12, SDR25, SDR50, SDR104 switching

characteristics parameters to show data is launched off of rising edge......................................................... 272

• (OSPI Switching Characteristics Table - Data Training): Updated cycle time for CLK to 6 ns (1.8 V) from 6.02

ns and 7.5 ns (3.3 V) from 7.52 ns for both SDR and DDR............................................................................278

• (OSPI Switching Characteristics - No Data Training SDR Mode ): Updated 3.3 V cycle time to 7.5 ns from

7.52 ns............................................................................................................................................................ 279

Changes from July 19, 2021 to July 21, 2021 (from Revision H (July 2021) to Revision I (July

2021)) Page

• (Nomenclature Description): Added device type "P" and "R"..........................................................................311

Changes from April 1, 2021 to July 19, 2021 (from Revision G (April 2021) to Revision H (July

2021)) Page

• （特性）：添加了用以阐明部分器件型号上的器件安全与安防/ASIL 的声明...................................................... 1

• (Device Comparison): Updated MSMC capacity for DRA829JM to 8MB. Updated Note 7 under Device

Comparison table to be generic. Added rows and footnotes clarifying certain safety and security feature are

available on select part number variants............................................................................................................ 7

• (Related Products): Updated link and description to Software Development Kit................................................9

• (Pin Attributes): Added the secondary pin multiplexing functions for the SERDES and controlled by

CTRLMMR regs................................................................................................................................................ 11

• (Signal Descriptions): Added note to clarify CPTS signal connection.............................................................110

• (Signal Descriptions): Moved MCU CPTS signals from CPSW2G to CPTS section. Moved SYNCn_OUT

signals from SYSTEM to CPTS section. Updated both sets of signal descriptions........................................ 111

• Updated description for VDDA_ADC0/1 to reference internal tie to VREFP.................................................. 131

• Added note specifying power balls must be supplied with voltage specified in Recommended Operating

Condition. .......................................................................................................................................................131

• (Pin Multiplexing): Updated PADCONFIG register address column to show actual address value and not

address offset value........................................................................................................................................135

• (Abs Max Ratings): Added Latch-Up Performance parameter values............................................................153

• Updated VDDS_DDR voltage rails min limits to 1.06 V in alignment with JEDEC spec. Updated description

for VDD_CPU AVS range. ............................................................................................................................. 156

• (MLB Electrical Characteristics table): Updated IOL/IOH=6 mA; VILSS=0.3*VDDIO; VIH=0.75*VDDIO. Added

slew rate information.......................................................................................................................................160

• (Electrical Characteristics tables): Updated eMMC PHY VILSS, VIHSS, VOL, VOH, IOL, IOH limits. ......... 160

• (Electrical Characteristics tables): Update ADC leakage for VSS to show negative current.......................... 160

• (Electrical Characteristics tables): Added Section headers to all electrical characteristics tables..................160

• Updated Power Supply Sequencing Section.................................................................................................. 171

• (Input and Output Clocks / Oscillators):Updated "Input Clocks Interface" image........................................... 192

• (WKUP_OSC0 Crystal Electrical Characteristics): Updated/Changed C

shunt

, ESR

xtal

= 80 Ω from "24MHz" to

now "25 MHz"................................................................................................................................................. 193

• (OSC1 Crystal Electrical Characteristics): Updated/Changed C

shunt

, ESR

xtal

= 80 Ω from "24MHz" to now "25

MHz"............................................................................................................................................................... 197

• Added WKUP_LFOSC0 startup time limi....................................................................................................... 201

• (Device Module Clock Frequencies): Renamed title and added references to TRM/DM sections describing

module clock and frequencies........................................................................................................................ 205

• (ATCLK[x] Switching Characteristics): Updated/Changed table information and associated ATCLK[x] Timing

figure...............................................................................................................................................................207

• Updated CSI-2 max freq support.................................................................................................................... 218

www.ti.com.cn

DRA829J, DRA829V

ZHCSN40J – FEBRUARY 2019 – REVISED AUGUST 2021

Submit Document Feedback

Product Folder Links: DRA829J DRA829V