5.2.4 Power Control ............................................................................................................. 228
5.2.5 Clock Control .............................................................................................................. 229
5.2.6 System Control ........................................................................................................... 238
5.3 Initialization and Configuration ..................................................................................... 245
5.4 Register Map .............................................................................................................. 246
5.5 System Control Register Descriptions (System Control Offset) ....................................... 253
6 Processor Support and Exception Module ........................................................ 515
6.1 Functional Description ................................................................................................. 515
6.2 Register Map .............................................................................................................. 515
6.3 Register Descriptions .................................................................................................. 515
7 Hibernation Module .............................................................................................. 523
7.1 Block Diagram ............................................................................................................ 525
7.2 Signal Description ....................................................................................................... 525
7.3 Functional Description ................................................................................................. 526
7.3.1 Register Access Timing ............................................................................................... 527
7.3.2 Hibernation Clock Source ............................................................................................ 527
7.3.3 System Implementation ............................................................................................... 530
7.3.4 Battery Management ................................................................................................... 531
7.3.5 Real-Time Clock .......................................................................................................... 531
7.3.6 Tamper ....................................................................................................................... 534
7.3.7 Battery-Backed Memory .............................................................................................. 537
7.3.8 Power Control Using HIB ............................................................................................. 537
7.3.9 Power Control Using VDD3ON Mode ........................................................................... 538
7.3.10 Initiating Hibernate ...................................................................................................... 538
7.3.11 Waking from Hibernate ................................................................................................ 538
7.3.12 Arbitrary Power Removal ............................................................................................. 539
7.3.13 Interrupts and Status ................................................................................................... 540
7.4 Initialization and Configuration ..................................................................................... 540
7.4.1 Initialization ................................................................................................................. 540
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 541
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 541
7.4.4 External Wake-Up from Hibernation .............................................................................. 542
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 543
7.4.6 Tamper Initialization ..................................................................................................... 543
7.5 Register Map .............................................................................................................. 543
7.6 Register Descriptions .................................................................................................. 545
8 Internal Memory ................................................................................................... 592
8.1 Block Diagram ............................................................................................................ 592
8.2 Functional Description ................................................................................................. 594
8.2.1 SRAM ........................................................................................................................ 594
8.2.2 ROM .......................................................................................................................... 594
8.2.3 Flash Memory ............................................................................................................. 596
8.2.4 EEPROM .................................................................................................................... 607
8.2.5 Bus Matrix Memory Accesses ...................................................................................... 613
8.3 Register Map .............................................................................................................. 613
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 616
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 642
8.6 Memory Register Descriptions (System Control Offset) .................................................. 659
5June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1292NCPDT Microcontroller
