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Tiva
™
TM4C1290NCZAD Microcontroller
DATA SHEET
Copyright © 2007-2014
Texas Instruments Incorporated
DS-TM4C1290NCZAD-15863.2743
SPMS430B
TEXAS INSTRUMENTS-PRODUCTION DATA
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are
registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/tm4c
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
WARNING – EXPORT NOTICE: Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as dened by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other
applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination
to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations
of dual-use goods in force in the origin and exporting countries, this technology is classied as follows:
■ US ECCN: EAR99
■ EU ECCN: EAR99
And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries.
June 18, 20142
Texas Instruments-Production Data
Table of Contents
Revision History ............................................................................................................................. 40
About This Document .................................................................................................................... 43
Audience .............................................................................................................................................. 43
About This Manual ................................................................................................................................ 43
Related Documents ............................................................................................................................... 43
Documentation Conventions .................................................................................................................. 44
1 Architectural Overview .......................................................................................... 46
1.1 Tiva™ C Series Overview .............................................................................................. 46
1.2 TM4C1290NCZAD Microcontroller Overview .................................................................. 47
1.3 TM4C1290NCZAD Microcontroller Features ................................................................... 50
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 50
1.3.2 On-Chip Memory ........................................................................................................... 52
1.3.3 External Peripheral Interface ......................................................................................... 54
1.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 56
1.3.5 Serial Communications Peripherals ................................................................................ 56
1.3.6 System Integration ........................................................................................................ 61
1.3.7 Advanced Motion Control ............................................................................................... 68
1.3.8 Analog .......................................................................................................................... 70
1.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 71
1.3.10 Packaging and Temperature .......................................................................................... 72
1.4 TM4C1290NCZAD Microcontroller Hardware Details ....................................................... 72
1.5 Kits .............................................................................................................................. 72
1.6 Support Information ....................................................................................................... 73
2 The Cortex-M4F Processor ................................................................................... 74
2.1 Block Diagram .............................................................................................................. 75
2.2 Overview ...................................................................................................................... 76
2.2.1 System-Level Interface .................................................................................................. 76
2.2.2 Integrated Configurable Debug ...................................................................................... 76
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 77
2.2.4 Cortex-M4F System Component Details ......................................................................... 77
2.3 Programming Model ...................................................................................................... 78
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 78
2.3.2 Stacks .......................................................................................................................... 79
2.3.3 Register Map ................................................................................................................ 79
2.3.4 Register Descriptions .................................................................................................... 81
2.3.5 Exceptions and Interrupts .............................................................................................. 97
2.3.6 Data Types ................................................................................................................... 97
2.4 Memory Model .............................................................................................................. 97
2.4.1 Memory Regions, Types and Attributes ......................................................................... 100
2.4.2 Memory System Ordering of Memory Accesses ............................................................ 101
2.4.3 Behavior of Memory Accesses ..................................................................................... 101
2.4.4 Software Ordering of Memory Accesses ....................................................................... 102
2.4.5 Bit-Banding ................................................................................................................. 103
2.4.6 Data Storage .............................................................................................................. 105
2.4.7 Synchronization Primitives ........................................................................................... 106
3June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1290NCZAD Microcontroller
2.5 Exception Model ......................................................................................................... 107
2.5.1 Exception States ......................................................................................................... 108
2.5.2 Exception Types .......................................................................................................... 108
2.5.3 Exception Handlers ..................................................................................................... 113
2.5.4 Vector Table ................................................................................................................ 113
2.5.5 Exception Priorities ...................................................................................................... 114
2.5.6 Interrupt Priority Grouping ............................................................................................ 115
2.5.7 Exception Entry and Return ......................................................................................... 115
2.6 Fault Handling ............................................................................................................. 118
2.6.1 Fault Types ................................................................................................................. 119
2.6.2 Fault Escalation and Hard Faults .................................................................................. 119
2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 120
2.6.4 Lockup ....................................................................................................................... 120
2.7 Power Management .................................................................................................... 121
2.7.1 Entering Sleep Modes ................................................................................................. 121
2.7.2 Wake Up from Sleep Mode .......................................................................................... 121
2.8 Instruction Set Summary .............................................................................................. 122
3 Cortex-M4 Peripherals ......................................................................................... 129
3.1 Functional Description ................................................................................................. 129
3.1.1 System Timer (SysTick) ............................................................................................... 130
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 131
3.1.3 System Control Block (SCB) ........................................................................................ 132
3.1.4 Memory Protection Unit (MPU) ..................................................................................... 132
3.1.5 Floating-Point Unit (FPU) ............................................................................................. 137
3.2 Register Map .............................................................................................................. 141
3.3 System Timer (SysTick) Register Descriptions .............................................................. 144
3.4 NVIC Register Descriptions .......................................................................................... 148
3.5 System Control Block (SCB) Register Descriptions ........................................................ 158
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 187
3.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 196
4 JTAG Interface ...................................................................................................... 202
4.1 Block Diagram ............................................................................................................ 203
4.2 Signal Description ....................................................................................................... 203
4.3 Functional Description ................................................................................................. 204
4.3.1 JTAG Interface Pins ..................................................................................................... 204
4.3.2 JTAG TAP Controller ................................................................................................... 206
4.3.3 Shift Registers ............................................................................................................ 207
4.3.4 Operational Considerations .......................................................................................... 207
4.4 Initialization and Configuration ..................................................................................... 210
4.5 Register Descriptions .................................................................................................. 210
4.5.1 Instruction Register (IR) ............................................................................................... 211
4.5.2 Data Registers ............................................................................................................ 212
5 System Control ..................................................................................................... 215
5.1 Signal Description ....................................................................................................... 215
5.2 Functional Description ................................................................................................. 215
5.2.1 Device Identification .................................................................................................... 216
5.2.2 Reset Control .............................................................................................................. 216
5.2.3 Non-Maskable Interrupt ............................................................................................... 223
June 18, 20144
Texas Instruments-Production Data
Table of Contents
5.2.4 Power Control ............................................................................................................. 224
5.2.5 Clock Control .............................................................................................................. 225
5.2.6 System Control ........................................................................................................... 233
5.3 Initialization and Configuration ..................................................................................... 240
5.4 Register Map .............................................................................................................. 241
5.5 System Control Register Descriptions (System Control Offset) ....................................... 248
6 Processor Support and Exception Module ........................................................ 504
6.1 Functional Description ................................................................................................. 504
6.2 Register Map .............................................................................................................. 504
6.3 Register Descriptions .................................................................................................. 504
7 Hibernation Module .............................................................................................. 512
7.1 Block Diagram ............................................................................................................ 514
7.2 Signal Description ....................................................................................................... 514
7.3 Functional Description ................................................................................................. 515
7.3.1 Register Access Timing ............................................................................................... 516
7.3.2 Hibernation Clock Source ............................................................................................ 516
7.3.3 System Implementation ............................................................................................... 519
7.3.4 Battery Management ................................................................................................... 520
7.3.5 Real-Time Clock .......................................................................................................... 520
7.3.6 Tamper ....................................................................................................................... 523
7.3.7 Battery-Backed Memory .............................................................................................. 526
7.3.8 Power Control Using HIB ............................................................................................. 526
7.3.9 Power Control Using VDD3ON Mode ........................................................................... 527
7.3.10 Initiating Hibernate ...................................................................................................... 527
7.3.11 Waking from Hibernate ................................................................................................ 527
7.3.12 Arbitrary Power Removal ............................................................................................. 528
7.3.13 Interrupts and Status ................................................................................................... 529
7.4 Initialization and Configuration ..................................................................................... 529
7.4.1 Initialization ................................................................................................................. 529
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 530
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 530
7.4.4 External Wake-Up from Hibernation .............................................................................. 531
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 532
7.4.6 Tamper Initialization ..................................................................................................... 532
7.5 Register Map .............................................................................................................. 532
7.6 Register Descriptions .................................................................................................. 534
8 Internal Memory ................................................................................................... 581
8.1 Block Diagram ............................................................................................................ 581
8.2 Functional Description ................................................................................................. 583
8.2.1 SRAM ........................................................................................................................ 583
8.2.2 ROM .......................................................................................................................... 583
8.2.3 Flash Memory ............................................................................................................. 585
8.2.4 EEPROM .................................................................................................................... 596
8.2.5 Bus Matrix Memory Accesses ...................................................................................... 602
8.3 Register Map .............................................................................................................. 602
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 605
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 631
8.6 Memory Register Descriptions (System Control Offset) .................................................. 648
5June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1290NCZAD Microcontroller
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